Conventional automatic speech recognition (ASR) models typically produce outputs as normalized texts lacking punctuation and capitalization, necessitating post-processing models to enhance readability. This approach, however, introduces additional complexity and latency due to the cascaded system design. In response to this challenge, there is a growing trend to develop end-to-end (E2E) ASR models capable of directly predicting punctuation and capitalization, though this area remains underexplored. In this paper, we propose an enhanced fully formatted E2E ASR model that leverages knowledge distillation (KD) through multi-codebook vector quantization (MVQ). Experimental results demonstrate that our model significantly outperforms previous works in word error rate (WER) both with and without punctuation and capitalization, and in punctuation error rate (PER). Evaluations on the LibriSpeech-PC test-clean and test-other subsets show that our model achieves state-of-the-art results.

Given a graph of the money transfers between accounts of a bank, how can we detect money laundering? Money laundering refers to criminals using the bank's services to move massive amounts of illegal money to untraceable destination accounts, in order to inject their illegal money into the legitimate financial system. Existing graph fraud detection approaches focus on dense subgraph detection, without considering the fact that money laundering involves high-volume flows of funds through chains of bank accounts, thereby decreasing their detection accuracy. Instead, we propose to model the transactions using a multipartite graph, and detect the complete flow of money from source to destination using a scalable algorithm, FlowScope. Theoretical analysis shows that FlowScope provides guarantees in terms of the amount of money that fraudsters can transfer without being detected. FlowScope outperforms state-of-the-art baselines in accurately detecting the accounts involved in money laundering, in both injected and real-world data settings.

The modular multilevel converters (MMC) has been investigated for a long time and has attracted increasingly more attentions due to its special topology. In order to generate more voltage levels with less power semiconductors for the MMC, this paper presented a novel topology of modular multilevel converters. There are two innovations for the proposed topology. 1. The current limiting inductance in each bridge arm is replaced by a split wound coupled inductor; 2. The sub-modules of the MMC is redesigned to further improve the performance of the system. Compare to the traditional sub-modules, the number of power semiconductors used in the newly designed sub-modules is reduced by half. The theoretical analysis shows that the number of output voltage levels of the proposed topology is increased from five levels to thirteen levels, thus the slew rate of the voltage (dv/dt) is suppressed and the total harmonic distortion (THD) is reduced. The simulation is also conducted in the paper which verified the correctness of the theoretical analysis.

The modular multilevel converters (MMC) has become an attractive research subject of power electronics due to its special topology. In this paper, a novel sub-module circuit for the MMC is proposed. Compared with the traditional sub-module circuits, the number of power semiconductors used in the proposed circuit is reduced by a quarter. Then, an improved three-phase multilevel topology is also constructed with the proposed sub-module circuit, accordingly, appropriate control logic is designed. The theoretical analysis shows that the line voltage of the proposed multilevel topology is increased from five levels to nine levels, thus suppressed the slew rate of the voltage (dv/dt). The simulation is also conducted in the paper which verified the correctness of the theoretical analysis.

A novel sub-module circuit is proposed in this paper based on the controllability theory. At first, traditional full bridge sub-modules (FBSM) of the MMC is modeled as a switched linear system, then controllability of the switched linear system model of the sub-module circuit is studied. It is found that the sub-module circuit is state controllable with only four operation modes adopted in the model. Therefore, a novel MMC sub-module circuit is designed to implement the required functionality of the MMC by removing the redundant power semiconductors. At last, the theoretic analysis and simulation results verified that the new MMC with the novel sub-modules is a 3n+1 level converter while the MMC with the traditional FBSM is only a n level converter. Hence the total harmonic distortion (THD) of the proposed MMC topology is much lower than the traditional one. Moreover, since the negative voltage states of the FBSMs are adopted to extend the output voltage range, the maximum output voltage of the MMC topology presented in this paper are increased by two hundred percent such that the dc voltage utilization ratio is improved. More importantly, the approach proposed in this paper can be easily used to redesign and simplify other power converter circuits.

The topology of modular multilevel converters (MMC) is investigated in this paper. First, single phase half bridge inverter with split wound coupled inductors was studied, it was found that more voltage levels can be generated by using split wound coupled inductors. Therefore, new MMC topology was proposed by the analysis result, therein, two more diodes were used for each arm, and split wound coupled inductors were applied to the modular multilevel converter (MMC) to replace the current-limiting inductors. The theoretic analysis and simulation results have verified that, the number of the voltage levels of modular multilevel inverter has increased from n levels to 2n-3 levels, thus slew rate of the voltage (dv/dt) was suppressed and the total harmonic distortion (THD) was reduced.

A novel space vector pulse width modulation strategy is proposed to reduce the switching frequencies of transistors in high-power inverters. The inverter is modeled as a switched linear system such that the controllability properties of the inverter can be investigated. After that, the 3-operation modes modulation strategy based on the m-modes controllability is proposed. With the 3-operation modes modulation technique, switching frequencies of the transistors can be reduced by one-third, therefore, the switching losses of the system can be reduced and the overall efficiency of the system can be improved. Finally, the simulation as well as experimental results verified the correctness of the approach.

This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at-speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device's defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.

In industry, chips become more and more complicated as advancing in deep submicron silicon process technology. LBIST can cover some newly emerging faults missed by traditional ATPG. That's why LBIST is becoming more and more popular. Besides launching LBIST through TAP interface, CPU launch LBIST feature may provide more flexibility for system-level or product testing and debugging. System engineer can easily kick-off LBIST with CPU interface instead of TAP.