On behalf of the Organizing Committee, it is our pleasure to welcome you to the 20thIEEE/ACM International Symposium on Low Power Electronics and Design, 2015, (ISLPED'15), held in Rome, Italy, on July 22–24, 2015. 20 years ago, a group of visionaries noted the avid interest in low-power design in many different disciplines and recognized the need to bring these diverse groups together with the goal of information sharing, and ISLPED was born. In this year's program, we mark the 20thanniversary of this conference with special awards, a new Industry Reception dinner, and a Founders' Panel.

This session consists of three industry papers invited for their viewpoints on the challenges on future needs for low-power electronic design from an industry perspective. The authors are experts on the field of low-power design techniques as well as in CAD tools for implementing these techniques, both areas that are critical to actually achieving the goals of aggressive chip design. In addition, the authors provide a perspective of the lessons learned and the evolution of the techniques that have enabled mobile platforms to become so widely deployed and a big part of our everyday lives.

Low-power EDA has come a long way in from its infancy almost 20 years ago, when the first low power tools for logic synthesis were introduced. Currently a large number of power-aware tools provide a spectrum of capabilities to address power issues, from analysis of power consumption and IR drops to automated power reduction during chip implementation. The most recent development is the advent of standards to specify power intent along with RTL which resulted in a number of new tools to help users implement and verify their power intent.

A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation whose result is not used in the downstream circuit, power is being consumed for an otherwise redundant computation. Operand isolation is a technique to minimize the power overhead incurred by redundant operations by selectively blocking the propagation of switching activity through the circuit. This paper discusses how redundant operations can be identified concurrently to normal circuit operation, and presents a model to estimate the power savings that can be obtained by isolation of selected modules at the register-transfer (RT) level. Based on this model, an algorithm is presented to iteratively isolate modules, while minimizing the cost incurred by RTL operand isolation. Experimental results with power reductions of up to 30% demonstrate the effectiveness of the approach.

Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements-buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity and common computational patterns in the algorithm to reduce the fan-outs and fan-ins of the interconnect wires, resulting in reduced bus capacitances and a simplified interconnect structure. Average power savings of 47% and 49% in buses and multiplexors, respectively, are demonstrated on a set of benchmark examples.

This work proposes an approach for high level design guidance for low power using properties of given algorithms and architectures. Several relevant properties (operation count, the ratio of critical path to available time, spatial locality, and regularity) are identified and discussed, with quantitative measures being proposed for the latter two. Significant emphasis is placed on exploiting the regularity and spatial locality algorithm properties for the optimization of interconnect power. Examples illustrate the large savings that can be attained through property-based guidance of algorithm selection and architecture composition. Though demonstrated for ASIC designs, this approach is extensible to different hardware platforms and performance metrics (e.g. speed, area).

The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area.>