Simulation is the most widely used tool for evaluating network protocols in multihop wireless networks, yet this has so far been limited due to a lack of models for creating a wide range of scenarios of mobile nodes moving about. For example, for evaluating multihop routing protocols, the frequently used Random Waypoint model can only effectively be used in scenarios with relatively high node density, as sparser configurations (e.g., The same nodes in a larger area) result in frequently or always partitioned networks, with no possible multihop path between many different pairs of nodes. In this extended abstract, we summarize the design and evaluation of the Random Controlled Sparse (RCS) mobility model, a new dynamic mobility model that can be controlled for a wide range of scenarios with varying levels of node sparsity or density while avoiding network partitions. Our goal is to be able to create mobile scenarios that expose previously unexplored areas of wireless protocol performance, particularly for multihop routing protocols. We evaluate the performance of the model in generating scenarios and demonstrate the sometimes surprising performance results that different degrees of node density have on example multihop wireless routing protocols.

The poster presents a novel and flexible architecture for deinterleaving combined pulse trains. Deinterleaving an interlaced pulse train arises in various areas of signal processing applications. Most of these applications require the identification of the main characteristics of pulse trains such as frequency. So far, most of the suggested algorithms for solving this problem are restricted to problems with several limiting assumptions. However, our design solves deinterleaving problem in a more general case by considering all the disturbing conditions such as jitter, dropped pulses, arbitrary start and end points, and a few number of existing pulses from one pulse train available. We used a modified version of sequential search for designing a parallel solution for deinterleaving problem. The proposed architecture utilized parallelism in order to achieve the best possible combination of accuracy and performance. This architecture employs several parameters in order to gain the desirable combination of accuracy, speed, memory usage and number of processing elements. Based on the situation and the value of disrupting stimulus, these parameters can be fixed to achieve the best possible trade-off between the major resource concerns. Simplicity and versatility of implementation on FPGA is one of the major points considered in this proposed architecture. Furthermore, FPGA infrastructure provides a convenient platform for implementing substantial parallel processing cores with arbitrary interconnections. On the other hand, considering the FPGA resource limitations, the total amount of available time and memory, we can fix the main parameters of this architecture to attain the best balance. Implementation of the architecture on a Xilinx Virtex-II FPGA and also analytical estimations show that the major concern for achieving the best accuracy is the limit on the total number of processing elements, not the amount of memory. This implies that we can gain more improvement in the accuracy in comparison to the amount of improvement in the speed