Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Sung-Yong Bang

dblp:82/3369 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 50% Embedded and real-time systems · 25% Performance modeling and evaluation · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › voltage scaling
dynamic voltage scaling
0.112009
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Energy-efficient computing
power management
0.112009
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Embedded and real-time systems
real-time scheduling
0.112009
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Performance modeling and evaluation › workload characterization › workload modeling
workload estimation
0.112009
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009

Methods — techniques the papers use, named apart from their topics

kalman filter · 0.1feedback control · 0.1
YearPublicationVenuePosition
2009 Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling
abstract
Dynamic voltage scaling (DVS) is a popular energy-saving technique for real-time tasks. The effectiveness of DVS critically depends on the accuracy of workload estimation, since DVS exploits the slack or the difference between the deadline and execution time. Many existing DVS techniques are profile based and simply utilize the worst-case or average execution time without estimation. Several recent approaches recognize the importance of workload estimation and adopt statistical estimation techniques. However, these approaches still require extensive profiling to extract reliable workload statistics and furthermore cannot effectively handle time-varying workloads. Feedback-control-based adaptive algorithms have been proposed to handle such nonstationary workloads, but their results are often too sensitive to parameter selection. To overcome these limitations of existing approaches, we propose a novel workload estimation technique for DVS. This technique is based on the Kalman filter and can estimate the processing time of workloads in a robust and accurate manner by adaptively calibrating estimation error by feedback. We tested the proposed method with workloads of various characteristics extracted from eight MPEG video clips. To thoroughly evaluate the performance of our approach, we used both a cycle-accurate simulator and an XScale-based test board. Our simulation result demonstrates that the proposed technique outperforms the compared alternatives with respect to the ability to meet given timing and Quality of Service constraints. Furthermore, we found that the accuracy of our approach is almost comparable to the oracle accuracy achievable only by offline analysis. Experimental results indicate that using our approach can reduce energy consumption by 57.5% on average, only with negligible deadline miss ratio (DMR) around 6.1%. Moreover, the average of computational overheads for the proposed technique is just 0.3%, which is the minimum value compared to other methods. More importantly, the DMR of our method is bounded by 11.7% in the worst case, while those of other methods are twice or more than ours.
Sung-Yong Bang, Kwanhu Bang, Sungroh Yoon, Eui-Young Chung
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1