The synthesis of Boolean functions is a process for converting some specification for circuit behavior into an expression (optimal in some sense) for a Boolean function. It has been conventional to specify this behavior by means of a table of combinations (or truth table) in which for each system of values for the input variables (i.e., input state) there is associated either the value 1 or the value 0 or the symbol d [1]. These are called, respectively, ONE states, ZERO states and DON'T CARE states. This specification then identifies a nonempty class of Boolean functions and the process of Boolean function synthesis is to select from this class of functions one capable of being represented most simply.

Logical circuits using Esaki diodes, and which are based on a principle similar to parametron (subharmonic oscillator element) circuits, are described. Two diodes are used in series to form a basic element called a twin, and a binary digit is represented by the polarity of the potential induced at the middle point of the twin, which is controlled by the majority of input signals applied to the middle point. Unilateral transmission of information in circuits consisting of cascaded twins is achieved by dividing the twins into three groups and by energizing each group one after another in a cyclic manner. Experimental results with the clock frequency as high as 30 mc are reported. Also, a delay-line dynamic memory and a nondestructive memory in matrix form are discussed.