FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S/sub RPU/ and a computational task represented by an acyclic data flow graph G=(V, E). Computations with logic area requirements that exceed S/sub RPU/ cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G=(V, E) such that each partitioned segment will not exceed S/sub RPU/ in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s/sub 1/,s/sub 2/,...,s/sub k/}, scheduling assigns a unique ordering S/sub i/-j,1/spl les/i/spl les/k,1/spl les/j/spl les/k, such that the computation would execute in proper sequential order as defined by the flow graph G=(V, E).

FPGA based custom computing machine applications have grown tremendously. Reconfigurable FPGAs incur very less reconfiguration times and also have the ability to reconfigure partially. They provide avenues to reuse the hardware resources at runtime, thus decreasing the hardware costs. In this paper, we present algorithms for temporal partitioning of applications into small size segments (under the area constraints), and scheduling of segments to ensure proper execution by satisfying the data dependencies among the segments. Our investigation concentrates on applications that are also directed acyclic graphs (DAGs). We have implemented the algorithms and have produced mappings of real applications on reconfigurable hardware.

In recent years, we have witnessed the rapid growth of reconfigurable computers. The first generation of reconfigurable computers consists of multiple FPGAs interconnected in a network. The computations are performed by partitioning an entire task into spatially interconnected sub-tasks. FPGAs used in the reconfigurable computers are programmed only once during the runtime of an executing application. FPGAs have the ability to reconfigure rapidly to any desired custom form. Reusing the FPGA resources during the application runtime can yield cost effective solutions for reconfigurable computing. Such runtime reconfiguration of FPGAs requires an efficient framework for the analysis and synthesis of the application and tools that handle the runtime reconfiguration. In this paper, we introduce the concept of temporal partitioning, to partition a task into temporally interconnected sub-tasks. We present algorithms and methodologies to analyze an application, and techniques to reuse the programmable hardware during the runtime of the application. Our approach has been successfully tested on read applications and has proven to be cost effective.