This paper presents a novel approach to compacting test response results for a multiple scan chains design. The compactors are based on (n+1, k) extended BCH code and guarantee detecting up to 2t single-bit errors and any odd number of single-bit errors, where n, k, t are integers depending on the particular BCH code used. Another technique uses controllable masks to handle any number of X's on test responses. The techniques have ability to detect more single-bit errors with minimum numbers of compactor outputs and can be used to reduce tester channels, test application time, and test data volume, independent of circuit under test (CUT) and fault models

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop's response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TC at the observation point.

A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also proposed. These cells maintain small delay variations for all input combinations, once minimum timing requirements on inputs are satisfied, and produce output pulses of fairly constant width for varying fanout, leaving enough headroom in the design to accommodate process, supply voltage, and temperature variations. These properties simplify the implementation of data-path and control circuits where the logic depth does not affect the stage output pulse width, eliminating the need for pulse-width controlling circuits required in previous works on SRL. In SRL, power is consumed only if new data are pumped through the logic. The clock grid is limited to the registers that launch and receive the signal path. The clocking overhead is thus reduced, compared with other dynamic designs, and it is especially suitable for wave pipelining. Case study examples and simulated characterization data are included to show the design methodology.

This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.

This paper presents a compression technique that reduces the test data volume while achieving high fault coverage within a Built-In Self-Test environment. The LFSR control data target only the RPR faults. The data are further reduced using a new code. Analysis of essential attributes of the control data is performed to assess their effect on the compression technique. The scheme was applied to several benchmark cores and indicated a superior effect than previously used compression techniques.

This paper reports the results of an extensive simulation to study the effect of body bias engineering on the performance of deep submicron technology circuits. Reverse body bias (RBB) is very useful in reducing a device's off-state leakage current and hence standby power. This reduction is more effective as the temperature increases. Forward body bias (FBB) suppresses short channel effects and hence improves V/sub t/ roll-off and reduces the gate delays. This improvement is enhanced as the power supply voltage decreases. However, the power dissipation and power delay product have increased under this biasing condition. A good strategy is to apply a forward body bias on critical path only to improve speed without significant increase in power dissipation.

This paper discusses a powerful experimental technique that makes it possible to examine the effect of logic block attributes on the block area density. The logic block is XOR-AND based, and five unique attributes were investigated. The experiment consisted of several iterations in which benchmark circuits were mapped on to various blocks, each varying in some attribute. Results are plotted on to a response contour map, indicating a point of maximum area density. The results have shown that inverting primary inputs to AND gates of the function structure is insignificant. In addition results indicate that two level function structures with an XOR output gate are able to contain logic in the smallest physical area.>

In integrated circuits, ground bounce is the voltage developed across the inductance of the power supply leads as a result of the current surge through switching gates. It causes distortion of circuit output waveforms that can interfere with testing. This paper describes a simple circuit model that can be used to estimate the ground bounce waveform that appears on both switching and nonswitching outputs of CMOS circuits as a result of ground bounce. The model includes the effects of several circuit parameters on the waveform and has been validated by extensive Spice simulation.

This paper describes the effects of gate-to-channel breakdown on the operation of BiCMOS logic gates. Both the static and dynamic behaviours of the gates are examined. The influence of the position of the defect within the channel is noted. Expressions for the logic levels and the quiescent current of an inverter in the presence of defects are calculated as an example. SPICE simulations confirmed the results and were used with other logic gates. The experimental results show that gate-to-channel breakdown cannot be modeled by a stuck-at fault. I/sub ddq/ testing is more effective than delay testing in detecting these effects. Test patterns for I/sub ddq/ are given.>

Digital testing is an emerging interdisciplinary branch of engineering. A solid foundation in the field requires good knowledge of calculus and discrete mathematics, and an awareness of the practical considerations encountered in actual testing of the digital systems. The balance of theory and practice within a digital testing course taught by the author is examined, and it is shown to be a function of the level of the course.>

An approach to quantify the digital testing system (DTS) attributes is presented. The quantification will help in determining criteria according to which benchmark circuits are selected. Two main parameters that can be used in the comparison are the speed of operation and memory requirements. Attempts are made to relate each of these two parameters to different attributes of the DTS. Experiments were carried out using a commercial automatic test-pattern generator to generate test sets for some ISCAS circuits. The results of the experiments are presented.>

A probabilistic model for pseudorandom testing of combinational circuits is presented. The expected fault coverage is shown to be accurately approximated as a series of exponentials that depends on the test length and the fault detectabilities. The derivations do not require the pattern generator to have the same number of stages as there are network inputs.>

This paper describes an analysis of system-detected errors on the MVS operating system under the eXtended Architecture (XA) for two IBM 3081 systems. The analysis classifies the errors in categories and examines the effectiveness of the recovery system of the MVS/XA. Comparison of the results for the two IBM 3081's confirm the dependence of the error distribution on the type of system utilization. The results for one of the machines are compared to those obtained for the same system when operating under MVS/SP. The comparison of the MVS/XA to the MVS/SP reveals the following: more addressing errors, a better error recording system and improved reliability and fault tolerance.

This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.