This paper presents the first experimental demonstration of fully Walsh-based wideband converters for Radio Frequency Front-End (RFFE) architecture implemented in 28 nm FDSOI CMOS technology. The system integrates a Walsh-based RF digital-to-analog converter (WDAC) and a Walsh-based RF analog-to-digital converter (WADC) designed for digital predistortion (DPD) applications. The WDAC achieves an instantaneous bandwidth of 4.7 GHz with an energy efficiency of 0.57 pJ/bit. The WADC achieves a 2.5 GHz bandwidth while consuming only 4 mW. The experimental demonstration showcase efficient wideband signal processing in the Walsh domain and highlights its potential as a promising paradigm for future low-power, high-throughput wireless transceivers, offering both wideband capabilities and a new order of scale energy efficiency.

Millimeter-wave bands open new bands of interest for ultra-high-speed wireless communications, but face technological bottlenecks such as power amplification. Working near the maximum oscillation frequency of the transistor leads to low intrinsic gain and low efficiency. Digital predistortion (DPD) achieves a higher power efficiency without degrading linearity. This paper presents a co-simulation workflow to design jointly DPD and the power amplifier (PA) in order to reach the optimum performances in linearity and power-added efficiency (PAE). The design of a PA at a center frequency of 142 GHz using the CMOS 28nm FDSOI technology from STMicroelectronics demonstrates how the design flow can take into account continuous wave (CW) and modulated signal simulations with and without DPD. The linearity performance is highlighted on the adjacent channel power ratio (ACPR) with an improvement of 4dB on an OFDM signal with 800 MHz bandwidth.

This paper investigates the use of Neural Network (NN) nonlinear modelling for Power Amplifier (PA) linearization in the Walsh-Hadamard transceiver architecture. This novel architecture has recently been proposed for ultra-high bandwidth systems to reduce the transceiver power consumption by extensive parallelization of the digital baseband hardware. The parallelization is achieved by replacing two-dimensional quadrature modulation with multi-dimensional Walsh-Hadamard modulation. The open research question for this architecture is whether conventional baseband signal processing algorithms can be similarly parallelized while retaining their performance. A key baseband algorithm, digital predistortion using NN models for PA linearization, will be adapted to the parallel Walsh architecture. A straighforward parallelization of the state-of-the-art NN architecture is extended with a cross-domain Knowledge Distillation pre-training method to achieve linearization performance on par with the quadrature implementation. This result paves the way for the entire baseband processing chain to be adapted into ultrahigh bandwidth, low-power Walsh transceivers.

A novel non-linear adaptive filter for the linearization of Radio Frequency (RF) Power Amplifiers (PAs) is presented. In this study, we aim at reducing the Digital Predistortion (DPD) complexity and enhancing its convergence speed for reduced computation time. The Walsh Transform is used as a computational basis for evaluating a predistorter (PD) model. The mathematical properties of the Walsh theory are exploited to adapt a memory polynomial (MP) in the sequency domain. A block-based Walsh LMS is introduced to seek the optimal PD coefficients. Simulations and results of linearization of class-AB PAs are exhibited. The comparison with conventional DPD algorithms shows that the proposed method converges 10 times faster with a reduction of 12% of the complexity for similar accuracy. Finally, a complete DPD architecture based on the Walsh Transform is proposed.

In the field of cognitive radio (CR), radio frequency (RF) transceivers must be efficient to save the terminal battery autonomy. Therefore, when designing the CR power amplifier (CR-PA), an obvious objective is to optimize efficiency over a large bandwidth. As a consequence, the CR-PA operates in its non-linear region and then frequency-dependent distortions are generated. This issue is all the more critical as one deals with high peak-to-average power ratio (PAPR) like those of OFDM signals. In this paper, we develop a digital post-distortion and detection technique in order to compensate the non-linearities generated by the CR-PA. It is based on a dynamic Volterra model to take into account the non-linear behavior of the CR-PA. The key feature of the proposed technique is the joint estimations of the model parameters and the CR-PA input samples. For this reason, an extended Kalman filter (EKF) is considered. However, as the model parameters can vary over time, several EKFs are combined by means of an interacting multiple model (IMM) algorithm. Simulation results confirm the relevance of the proposed postdistortion and detection technique.

For a battery driven terminal, the power amplifier (PA) efficiency must be optimized. Consequently, non-linearities may appear at the PA output in the transmission chain. To compensate these distortions, one solution consists of using a digital detector based on a Volterra model of both the PA and the channel and a Kalman filter (KF) based algorithm to jointly estimate the Volterra kernels and the transmitted symbols. Here, we suggest addressing this issue when dealing with cognitive radio (CR). In this case, additional constraints must be taken into account. Since the CR terminal may switch from one sub-band to another, the PA non-linearities may vary over time. Therefore, we propose to design a digital detector based on an interacting multiple model combining various KF based estimators using different model parameter dynamics. This makes it possible to track the time variations of the Volterra kernels while keeping accurate estimates when those parameters are static. Furthermore, the single and multicarrier cases are addressed and validated by simulation results. Our solution corresponds to a compromise between computational cost and bit-error-rate performance.

This paper presents a 65 nm CMOS power amplifier (PA) using a coupled transformer. The PA is based on an original structure, called stacked folded fully differential structure (SFFDS). It is applied to the UMTS W-CDMA standard. The parallel SFFDS power amplifier provides 30.5 dBm of output power with 20% of power added efficiency (PAE) at 1.95 GHz. The output compression point (OCP1) is 27.5 dBm and the PA is linear up to 24 dBm in order to meet the maximum output power required by the UMTS W-CDMA standard.

This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65 nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W-CDMA requirements, especially on output power with regards to efficiency to save battery life, the used PA is a two-stage Class E PA. The output 1 dB compression point (CP1) is 22 dBm and Power Added Efficiency (PAE) @CP1 is 55.1%. This PA is then included in a loop to realize oscillation condition. The Power VCO oscillates @ 1.95 GHz, achieves an output power of 23.3 dBm with 60.3% PAE.