Compute-in-memory (CIM) for edge devices is usually constrained by on-chip resources, including on-chip memory and physical chip size, which hinders the deployment of more complex neural networks. By leveraging the sparsity of neural networks, the overall memory requirements and energy consumption can be reduced. However, Existing sparsity-aware architectures cannot achieve high energy efficiency due to off-chip sparsity control. This work proposes:1) Hybrid sparsity regulation strategy. The sparsity encoding and alignment circuit is designed and implemented, realizing on-chip sparsity detecting and encoding. 2) Sparsity-aware compute-in-memory (CIM) array based on RRAMs. The in-situ deployment of unstructured sparsity is implemented inside the CIM array, and the CIM array and sparsity are tightly coupled by sparsity read/write. This work demonstrates the design and evaluation of SA-CIM: a sparsity-aware CIM macro with 16Mb RRAM with fine-grained sparsity detecting and encoding capacity, achieving energy efficiency of 22.7TOP/W@8b/8b.

RRAM-based Compute-in-memory (CIM) has emerged as a promising computing paradigm for artificial intelligence (AI) algorithms. However, the low on/off ratio and high on-current have been the major challenges to enhance the accuracy, parallelism, and energy efficiency. In this paper, we propose a novel Hybrid RRAM-Capacitor (HRC) cell based CIM macro to address these issues. The proposed HRC cell achieves a high on-off ratio with sub-100nA on-current and eliminates direct current path during computation, which significantly enhances both parallelism and energy efficiency. The write-verify scheme for RRAM programming is optimized for HRC cell array, and is further supported by a quantization result calibration technique using a dummy column to ensure high linearity and accuracy in analog domain multiply-and-accumulate (MAC) operations. A HRC-CIM macro has been designed and demonstrated using 28nm technology node, enabling block-level parallelism across 64 rows with 4-bit input per row, and delivering an energy efficiency of up to 40.40 TOPS/W @8b-IN/8b-W.

Current diagnostic approaches for macular degeneration in optical coherence tomography (OCT) images often lead to misdiagnosis due to their limited ability to capture the disease’s multiscale and irregular features. We present PDC-DETR, a Parallel Dilated Convolutional Detection Transformer, which introduces three major innovations for accurate and efficient macular degeneration analysis. First, a Parallel Feature-Optimized Attention Pyramid Network (PFOAPN) enables simultaneous modeling of global context and local details through multi-scale feature pathways. Second, a novel Wise-MPDIoU loss dynamically adjusts to variations in image quality while improving lesion localization accuracy. Third, the lightweight design ensures real-time clinical applicability, requiring only 38.2 MB parameters and 58.5 GFLOPs, while achieving 94.1% accuracy across five macular degeneration categories at 71 FPS. This study establishes a new benchmark for automated OCT-based retinal disease detection, providing both high diagnostic accuracy and practical clinical deployment potential.