In this paper, a novel 3D CMOS nanohybrid technology, 3D CMOL, is introduced to establish FPGA chips. By combining two leading technologies, hybrid CMOS/nanoelectronic circuit (CMOL) and 3D integration, 3D CMOL can provide a feasible and more efficient fabrication/assembly process than the existing 2D CMOL. Furthermore, 3D CMOL FPGA implements circuits in three dimensions so that it can increase the density of the nanodevices and achieve higher performance compared to 2D CMOL and field programmable nanowire interconnect (FPNI). This paper presents the architecture optimization, 3D integration, defect tolerance, and performance evaluation of 3D CMOL FPGA. It is expected that this technology can lead to technology breakthroughs towards the development of the next FPGA generation.

New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case studies, two efficient on-line multipliers are implemented using the new full adders, providing improved performance while requiring lower number of transistors.

In this paper, an efficient immunity method is proposed for two-prime RSA cryptosystem against hardware fault attack. The proposed system has more immunity than the previous system and is targeted for FPGA implementation. For the 32-bit signing case, the proposed method is 15% faster than the previous design while requiring only 70% of the hardware resource.