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Steven C. Chan

dblp:82/5443 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorHuman-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Integrated circuit design · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.012002
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation
hardware verification and test
0.012002
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Integrated circuit design › semiconductor devices
silicon-on-insulator
0.012002
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Electronic design automation › hardware verification and test
static noise analysis
0.012002
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002

Methods — techniques the papers use, named apart from their topics

transistor-level noise analysis · 0.0state-diagram abstraction · 0.0
YearPublicationVenuePosition
2003 Design of Resonant Global Clock Distributions
abstract
We present a new approach to global clock distribution in which traditional tree-driven grids are augmented with on-chip inductors to resonate the clock capacitance at the fundamental frequency of the clock node. Rather than being dissipated as heat, the energy of the fundamental resonates between electric and magnetic forms. The clock drivers must only provide the energy necessary to overcome losses. As a result, power reduction of over 80% is possible depending on the Q of the resonant system. Clock latency is also improved because the effective capacitance of the grid is lower, and fewer buffer stages are necessary to drive the grid. Skew and jitter reductions come about because of this reduced buffer latency.
Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
ICCD1
2002 Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology
abstract
This paper extends transistor-level static noise analysis to consider the unique features of partially depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable regular switching activity. Results are presented using a commercial static noise analysis tool incorporating these extensions and comparisons are made with SPICE.
Steven C. Chan, Kenneth L. Shepard
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2001 Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits
abstract
Inductance and inductive crosstalk has become an important new concern for on-chip wires in deep-submicron integrated circuits. Recent advances in extractors to include inductance make possible the extraction of coupled RLCK interconnect networks from large, complex on-chip layouts. We describe the techniques we use in a commercial static noise analysis tool to analyze crosstalk noise due to fully-coupled RLCK networks extracted from layout. Notable are the approaches we use to filter and lump aggressor couplings, as well as the techniques used to handle degeneracies in the modified nodal analysis (MNA)formulation. Furthermore, the nonmonotonicity of interconnect responses in the presence of inductance require additional "sensitizations" in searching the possible switching events inducing the worst-case noise. Comparisons with silicon indicate the need to include the substrate in the extracted models in certain cases.
Steven C. Chan, Kenneth L. Shepard
ICCAD1
2000 Design and performance evaluation of mixed manual and automated control traffic
abstract
We present a technology which allows manually controlled and automatically controlled vehicles to co-exist, thereby reducing much of the cost and infrastructure requirements in highway automation. An autonomous vehicle driving system (AVDS) is presented which only uses information from vehicle sensors, thereby eliminating the requirement that vehicles communicate with one another. This format allows gradual market penetration of AVDS, which makes the technology attractive from a systems implementation standpoint. To evaluate the performance of the mixed traffic, we simulate manual and automated vehicles together and show that our AVDS can lead to potentially large gains in capacity and smoother flow without the loss of safety.
Sunan Huang 0001, Wei Ren 0009, Steven C. Chan
IEEE Trans. Syst. Man Cybern. Part A3