We propose SPADES, the first sparse matrix vector multiplication (SpMV) accelerator incorporating online GZIP decompression. The goal of the decompression is to reduce off-chip data movement, which has become a major source of energy consumption in SpMV accelerators. Our proposed GZIP-SpMV flow achieves an average compression ratio of 3.36 for the sparse matrix CSC data, reducing the off-chip data traffic by 70%. We fabricated SPADES in TSMC 28-nm with a die area of 2.47 mm2. Compared with the prior SpMV accelerator, SPADES achieves 2.32X better energy efficiency.

We tackle the important problem class of solving nonlinear partial differential equations. While nonlinear PDEs are typically solved in high-performance supercomputers, they are increasingly used in graphics and embedded systems, where efficiency is important.

Due to the end of supply voltage scaling and the increasing percentage of dark silicon in modern integrated circuits, researchers are looking for new scalable ways to get useful computation from existing silicon technology. In this paper we present a reconfigurable analog accelerator for solving systems of linear equations. Commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty in programming are all compensated for using methods we discuss. Based on a prototyped analog accelerator chip we compare the performance and energy consumption of the analog solver against an efficient digital algorithm running on a CPU, and find that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design. Due to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint. Finally, we conclude that problem classes outside of systems of linear equations may hold more promise for analog acceleration.

A variable-rate digital signal processor capable of processing samples with a variable sampling rate is discussed in this paper. The clock rate in the DSP tracks the input sampling rate. Compared to a fixed-rate DSP, the proposed one has a lower output data rate and thus consumes less power for computation. A reconstruction filter with a variable cutoff frequency is used to reconstruct the output. It is shown that the signal-to-noise ratio remains fixed when the sampling rate is changed.

The use of voltage-controlled ring oscillators to implement analog integrators with high DC gain has been recently proposed and successfully demonstrated in analog filters and amplifiers. Such an implementation encodes an analog input in a pulse-width-modulated form. We consider direct processing of such signals with a clockless, event-driven, continuous-time DSP. We demonstrate through simulations that the resulting highly-digital system can have significantly relaxed DSP constraints over ones that encode analog signals using level-crossing sampling, potentially lowering the power dissipation and chip area of the processor significantly. Nonidealities and design considerations are also discussed.

A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they have suboptimal energy for low- and varyingrate input streams. We introduce a complete methodology for designing reconfigurable delay lines that dynamically adapt their granularity to actual input traffic, on-the-fly, without stalling or disturbing normal operation. Two or more modes can be used, with different granularities to handle different traffic densities. During sparser traffic, the system is reconfigured to the proper coarser-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is one promising domain, continuous-time digital signal processors (CT DSPs), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. Design approaches for bimodal and trimodal adaptive lines are presented, which are then implemented in a 0.13-μm IBM CMOS technology. Simulations for these delay lines demonstrate savings in overall dynamic power up to 45.5% and 71.1%, respectively, when compared with a nonadaptive design, with only minimal area overhead (1.5% and 3%, respectively, for a targeted configuration). Using extensions to more configuration modes, further power reductions can be achieved. While results are presented for CT DSPs, significant benefits are also expected in many other domains, where the delay lines are used.

A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst-case input rate. However, due to their rigid structure, they have sub-optimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines which dynamically adapt granularity to traffic, on-the-fly, without stalling or disturbing normal operation. These lines have two modes: coarse- and fine-grain. During sparser traffic, the system is reconfigured to coarse-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is on one promising domain, continuous-time digital signal processors (CT DSP's), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. With a complete implementation in a 0.13 um IBM CMOS technology, post-layout simulations demonstrate an average overall dynamic power reduction up to 45.5% compared to a non-adaptive design, with only minimal area overhead. The design methodology is modular, supporting extensions to multiple configuration modes to provide even greater power reduction for a variety of input traffic. While results are presented for CT DSP's, significant benefits are also expected in many other domains where delay lines are used.

We present techniques for processing MPEG-audio encoded signals during the decoding process, using efficient fixed-point arithmetic operations. A large signal-to-quantization-noise-ratio is achieved over a large range of input levels. By taking advantage of MPEG audio built-in properties, quantization distortion at the outputs of our systems is kept largely inaudible, even though only low-resolution fixed-point operations are used in the processing.

This paper proposes an energy-efficient asynchronous tunable delay element architecture, appropriate for low-to high-speed digital applications. The delay is made controllable via control currents. The presented delay cell improves upon the efficient thyristor-like-based circuits in prior art by reusing the charge supplied on one edge of the input during the next edge of the input. Over 50% energy reduction is achieved.

We present a tutorial review of digital signal processing in continuous time, and associated analog-to-digital conversion. The systems presented do no utilize a clock and are fully event-driven, with power dissipation that adapts to the input signal automatically. An integrated view of several related techniques is offered.

A variable-bit quantization scheme is proposed for use in the context of continuous-time digital signal processing, with resolution depended on signal speed. It is shown that a decrease in resolution for fast inputs does not corrupt the inband spectrum, while leading to power savings. Analysis and extensive simulations are provided.

This paper treats signals encoded using level crossing sampling. Such encoding makes possible a variable sampling rate; fast-varying parts of the signal are sampled fast, while slowly-varying parts of the signal are sampled slowly. We propose a technique for processing such signals, which results in an output with very low error. With 4 bits of amplitude quantization, the signal-to-error ratio is better than 100 dB.

We extend the technique of instantaneous companding (compressing and expanding) to digital signal processors (DSPs). Companding has been used for many years in non-dynamical channels, but the dynamical nature of DSPs causes output distortion in standard implementations of companding, where a compressor and expander are used at the input and output, respectively, without additionally modifying the DSP. In the proposed technique, we specify a method for combining input compression, output expansion, and application of nonlinear functions internal to the DSP, all in a manner transparent to the input-output characteristics of the DSP and its A/D interfaces, thus eliminating distortion in the final analog output. As a result, all the signals involved span most of the available bits, resulting in significant improvement in quantization errors and signal-to-noise-plus-distortion ratios over a large input range. The theory is supported by simulation and subjective listening tests.

Continuous-time digital signal processors avoid sampling, and thus do not suffer from aliasing of the signal, or of aliasing down of out-of-band distortion components, arising from quantization, into the band of interest. The reduction of in-band distortion is derived analytically for certain symmetric inputs and is discussed for input processes with a Gaussian amplitude probability density function. It is demonstrated that processing in continuous time yields a 9 dB improvement of in-band signal-to-distortion ratio per added bit of quantizer resolution for both input classes examined, compared to a 6 dB per bit improvement in sampled systems.

We discuss a technique whereby internal signals in a DSP can be controlled externally without causing output disturbances. This is used to extend the technique of companding (compressing and expanding), widely used in transmission and sound recording, to digital signal processors. It is shown that this technique allows all signals involved, including those at the input of an analog-to-digital converter and those internal to a fixed-point DSP, to be close to full scale, thus spanning most of the available bits and making possible a large signal-to-noise-plus-distortion ratio over a large input range.

The operation of digital signal processors in continuous time is discussed. It is shown that the main advantages of digital arithmetic can be maintained in such operations, while aliasing of the signal and the quantization error is avoided altogether. Continuous-time operation makes possible a smaller number of bits for a given signal-to-quantization error ratio. Simulation results are presented.

A fuzzy logic controller has been realized using mixed analog-digital CMOS very large scale integration (VLSI) circuits for application in cases where the input and output variables are in analog form. It employs a new architecture where time sweeping of variables allows continuous-amplitude evaluation of fuzzy inferences and defuzzification during each evaluation cycle without having to discretize input and output variables. Direct processing of the analog input signal is used to obtain the corresponding crisp value; the digital portion is used only for programmability. No A/D and D/A converters are needed. The controller can handle three inputs, one output, and 25 programmable fuzzy rules. The test IC chips were fabricated using 0.7-/spl mu/m CMOS technology. A control problem of stabilizing a ping-pong ball in a tube with a controllable air flow has been successfully demonstrated.

In this paper we discuss a method for making possible the active parallel-mode compensation of on-chip inductor and capacitor losses, and for making both the quality factor and the inductance value electronically tunable. The application of this technique in filters is emphasized throughout, and is demonstrated in a 2nd-order bandpass filter. The paper provides analytical results, discusses transistor-level circuits and presents experimental results from a linearity test on a breadboard.>

We formulate the state equations for tme- and frequency-domain aalysis of switched-capacitor networks (SCN's) using charges associated with topologically identifiable structures in a network as network variables. The method effectively combines variable elimination to reduce matrix sizes with redundancy elimination to reduce memory requirements for many-phases SCN's. The frequency-domain analysis equations are formulated in such a way that computation can be done in a simple iterative manner akin to time-domain analysis but without using discrete Fourier transform. Two speed-up algorithms based on the proposed formulation for input and output sampling are presented.

This paper summarizes the inadequacies of present MOSFET models as applied to analog circuit design and, in some cases, proposes solutions. Both efficient models suitable for CAD and more complex models are considered. Problem areas discussed include poor modeling of the moderate inversion region, poor modeling of the surface potential in strong inversion, ambiguous use of "threshold" voltages and poor expressions for them, poor modeling of the drain small-signal conductance, very poor modeling of intrinsic small-signal capacitances, inadequate small-signal equivalent circuit topologies, and poor implementation of known correct ideas in some CAD programs, including the dependence of the effective mobility on the substrate potential, the modeling of thermal noise in the nonsaturation region, and the modeling of ion-implanted devices.