The charge-redistribution data converter topology is constructed from an array of parallel-connected capacitors with a specific capacitor ratio, and is a fundamental component of successive approximation register (SAR)-analog-to-digital converter (ADC) architectures. This paper presents complementary placement and routing algorithms for such capacitor arrays with the goal of nonlinearity minimization in the target SAR-ADC architecture. Starting from a state-of-the-art static nonlinearity model and its accompanying placement method, generalizations are made for both binary- and nonbinary-weighted capacitor ratios. Taking the generalized nonlinearity model and capacitor routing complexity into consideration, an improved placement method was developed, augmented with a matching-based routing technique driven by routing length adjustment. Analytical results compare the new methodology to the state-of-the-art, achieving superior resolution, linearity, and area.

This paper presents a new approach to capacitor placement in differential charge-scaling data converters. Good capacitor matching is crucial for charge-scaling converter resolution. Differential circuits are preferred to single-ended architectures due to improved immunity to noise and variations. The proposed method is based on the analysis of converter static nonlinearity equations. The impact of capacitor variations on converter linearity is minimized by exploiting spatial correlation between devices. Mathematical analysis is completed for two differential analog-to-digital converters. A procedure to obtain a capacitor placement is presented for each circuit. The architectures are compared with respect to linearity and capacitor placement area.

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a novel analytical model for the linearity metrics of a charge scaling digital-to-analog converter. Minimizing the variance of the linearity metrics directs a new chessboard placement method for the capacitor array. Chessboard placement is shown to be superior to the state of the art in consideration of both random and systematic mismatch. The new analytical model is then used to develop a flow for capacitor array sizing.

A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values. The flow is driven by design, placement, and routing constraints-no layout template is necessary. Every possible layout for each device in the circuit is investigated; the layouts with the best geometric features and smallest quantization error (due to manufacturing grid alignment) are kept. For circuit placement, a complete enumeration of possible circuit placements, limited only by usual constraints of symmetry, proximity, and common centroid, is performed. Out of this enumeration a final circuit placement is selected and routed. The new flow is integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing; layouts are synthesized during both gradient approximation and next step determination. Layout-driven circuit sizing was applied to two example circuits. Sizing of the first circuit example took 8× the amount of CPU time needed for traditional circuit sizing, but remained feasible at 2.1 h of wall clock time on a contemporary workstation.

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.