Demo Data from EDBT 2026 / reviewers in the wild / expert
Ming-Tak Leung
dblp:82/6416
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 77% Integrated circuit design · 23% | |
| Artificial intelligence
1 paper |
Probabilistic and Bayesian machine learning · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Probabilistic and Bayesian machine learning
boltzmann machine |
0.0 | 1 | 1993 | Digital Boltzmann VLSI for Constraint Satisfaction and Learning · NIPS 1993 |
Hardware accelerators and domain-specific architectures
constraint satisfaction |
0.0 | 1 | 1993 | Digital Boltzmann VLSI for Constraint Satisfaction and Learning · NIPS 1993 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1993 | Digital Boltzmann VLSI for Constraint Satisfaction and Learning · NIPS 1993 |
Methods — techniques the papers use, named apart from their topics
boltzmann machine · 0.0VLSI · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Digital Boltzmann VLSI for Constraint Satisfaction and Learning
Michael Murray, Ming-Tak Leung, Kan Boonyanit, Kong Kritayakirana, James B. Burr, Gregory J. Wolff, Tokahiro Watanabe, Edward L. Schwartz, David G. Stork, Allen M. Peterson |
NIPS | 2 |
| 1992 | Deterministic Boltzmann machine VLSI can be scaled using multi-chip modulesabstractDescribes a special purpose, very high speed, digital deterministic Boltzmann neural network VLSI chip. Each chip has 32 physical neural processors, which can be apportioned into an arbitrary topology (input, multiple hidden and output layers) of up to 160 virtual neurons total. Under typical conditions, the chip learns at approximately 5*10/sup 8/ connection updates/second (CUPS). Through relatively minor (subsequent) modifications, the authors' chips can be 'tiled' in multi-chip modules, to make multi-layer networks of arbitrary size suffering only slight communications delays and overhead. In this way, the number of CUPS can be made arbitrarily large, limited only by the number of chips tiled. The chip's high speed is due to massively parallel array computation of the inner products of connection weights and neural activations, limited (but adequate) precision for weights and activations (5 bits), high clock rate (180 MHz), as well as several algorithmic and design insights.> Michael Murray, James B. Burr, David G. Stork, Ming-Tak Leung, Kan Boonyanit, Gregory J. Wolff, Allen M. Peterson |
ASAP | 4 |
| 1990 | Fingerprint processing using back propagation neural networksabstractA system for the extraction of minutiae from gray-scale fingerprint images using back-propagation networks and Gabor filters is described. Good detection ratios and low false alarm rates were achieved. The importance of having good input representations of the image data is illustrated through variations in the performance of different trained networks. The usefulness of Gabor filters in the representation processing layer is demonstrated Ming-Tak Leung, W. E. Engeler, P. Frank |
IJCNN | 1 |