Context-based binary arithmetic coding (CBAC) is an entropy coder of AVS 2.0, the latest Chinese video compression standard for 8K ultra-high-definition (UHD) video, which employs a logarithmic number system to avoid multiplication operations for range updates for binary arithmetic coding (BAE). In this paper, we propose a high-throughput CBAC hardware encoder for 8K UHD. To enhance its throughput, we introduce a bin-merging technique that converts a subsequence of bins into a merged bin without affecting the functionality of the CBAC encoder. Moreover, we also employ a 4-stage pipeline architecture for CBAC and lookup tables for context updates. Consequently, the proposed CBAC encoder can process about 3.94 bins per cycle and achieve a throughput of 2.9 Gbins per second. When synthesized in a TSMC 65nm LP process, it operates up to 735 MHz and the total gate count is 182.5 K. To the best of our knowledge, this is the highest throughput for a CBAC encoder.

Although advanced motion vector prediction (AMVP) modes based on motion estimation (ME) are selected significantly less due to the merge mode newly adopted in the high-efficiency video coding (HEVC), integer ME (IME) still occupies a large amount of computation in HEVC because the HEVC supports a highly flexible block partitioning structure. Introduction of the merge mode in HEVC substantially affects the optimal search algorithm of IME. Therefore, this gives a chance to reduce the computational complexity of ME with marginal drop of the compression efficiency. This paper proposes a new IME algorithm that significantly reduces its search ranges. Computational complexity of the proposed algorithm is reduced without serious degradation in coding efficiency by obtaining additional accurate motion vector predictors (MVPs) in a bottom-up order and searching narrow regions around multiple MVPs. These bottom-up MVPs are obtained from the prediction units (PUs) in the coding units (CUs) in the hierarchically lower level, which share the pixel area either completely or partially with the current PU. Although the encoder should perform the proposed IME in a bottom-up order from the smallest CUs to the larger CUs, several other processes, such as fractional ME and merges mode are performed in a top-down order to exploit several fast algorithms already adopted in the HEVC test model encoder. To keep compatibility with HEVC standard, the bottom-up MVPs are utilized for only IME. The bitstream is generated using standard AMVP. According to the simulation results, it is confirmed that the proposed algorithm improves the accuracy of MVPs, which leads to the reduction of IME computational complexity up to 81.95% on average with the Bjøntegaard delta bitrate of 0.39%.

In this paper we compare the coding efficiency of AVS 2.0[1] for engines of the Context-based Binary Arithmetic Coding (CBAC)[2] in the AVS 2.0 and the Context-Adaptive Binary Arithmetic Coder (CABAC)[3] in the HEVC[4]. For fair comparison, the CABAC is embedded in the reference code RD10.1 because the CBAC is in the HEVC in our previous work[5]. The rate estimation table is employed only for RDOQ in the RD code. To reduce the computation complexity of the video encoder, therefore we modified the RD code so that the rate estimation table is employed for all RDO decision. Furthermore, we also simplify the complexity of rate estimation table by reducing the bit depth of its fractional part to 2 from 8. The simulation result shows that the CABAC has the BD-rate loss of about 0.7% compared to the CBAC. It seems that the CBAC is a little more efficient than that the CABAC in the AVS 2.0.

In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from one source, LTL property. We constructed LTL-to-TRS, which is translator from LTL property sets to Bluespec term-rewriting system (TRS) description. And, we use a Bluespec compiler as a synthesizer from TRS to RTL. Also, to match the implementation with the formal specification, we use a VIS solver as a model checker. And then, channel instances generated by proposed design method are transformed into channel template-generators for communication channel library. These channel templates can be used in DSE process in SoC design flow.

System-level design methodologies have been introduced as a solution to handle the design complexity of embedded multiprocessor SoC (MPSoC) systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: Simulink Combined Algorithm and Architecture Model (CAAM), Virtual Architecture, Transaction-accurate Model and Virtual Prototype. We used two multimedia applications, Motion-JPEG and H.264, to evaluate this design flow. Experimental results show that our design flow can generate various MPSoC architectures from Simulink CAAM correctly and efficiently, allowing processor and task design space exploration at different abstraction levels.

Heterogeneous MPSoCs present unique opportunities for emerging embedded applications, which require both high-performance and programmability. Although, software programming for these MPSoC architectures requires tedious and error-prone tasks, thereby automatic code generation tools are required. A code generation method based on fine-grain specification can provide more design space and optimization opportunities, such as exploiting fine-level parallelism and more efficient partitions. However, when partitioned, fine-grain models may require a large number of inter-processor communications, decreasing the overall system performance. This paper presents a Simulink-based multithread code generation method, which applies Message Aggregation optimization technique to reduce the number of inter-processor communications. This technique reduces the communication overheads in terms of execution time by reduction on the number of messages exchanged and in terms of memory size by the reduction on the number of channels. The paper also presents experiment results for one multimedia application, showing performance improvements and memory reduction obtained with Message Aggregation technique.

Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent compilation and support multiple video standards and a shorter time-to-market. To find an efficient SW code for the multiple core architecture for a video codec application, it is very important to easily explore the design space by generating a SW code automatically from its functional model. We introduce Abstract Clock Synchronous Model (ACSM) for functional modeling of video codec applications. The ACSM can easily represent both parallelism and conditionals, which are common in video codec applications. By applying ACSM to an H.264 baseline decoder on single core architecture, we reduced the execution time and the number of external memory accesses by 32 % and 46 % respectively compared to traditional dataflow model.

We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the component designers describe mainly the computation part of the component, and the system designer can construct the communication part by using our refinement-based design environment. Moreover, we introduced a concept of the communication architecture template tree (CATree), which helps IP designers to effectively separate computation and communication for a system function. We confirmed that this approach is effective by applying it to a H.264 decoder design.

Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and control-dependent, memory optimization based on global and precise analysis of data and control dependency is required. We generate a memory-efficient C code from a restricted Simulink model, which can represent both data and control dependency explicitly, by applying two buffer memory optimization techniques: copy removal and buffer sharing. Copy removal is performed while parsing the Simulink model. Buffer sharing requires global scheduling and formal lifetime analysis. Experimental results on an H.264 video decoder show that the buffer memory size and execution time of the C code generated by the proposed method are 71% and 32% less than those of the C code produced by Simulink's C code generator, respectively. When compared to the hand written C code, the memory size was reduced by 27% while its execution time was increased by only 3%.

We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16x16 PE array, an adder tree and comparators to find all 41 motion vectors and their minimum SADs for the blocks of 16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4. It employs a 2-D datapath and its control of the search area data is simple and regular. The proposed VBSME can achieve 100% PE utilization by employing a preload register and a search data buffer inside each PE and allow real-time processing of 4CIF(704x576) video with 15 fps at 100 Mhz for a search range of [-32~+31].

We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25μm CMOS technology. Its minimum energy consumption of 4.67μA/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version.

Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computation to be handled. The key issue that needs to be solved is then how to manage data transfers between large numbers of distributed memories. To overcome this issue, our paper proposes a scalable Distributed Memory Server (DMS) for multiprocessor SoC (MPSoC). The proposed DMS is composed of: (1) high-performance and flexible memory service access points (MSAPs), which execute data transfers without intervention of the processing elements, (2) data network, and (3) control network. It can handle direct massive data transfer between the distributed memories of an MPSoC. The scalability and flexibility of the proposed DMS are illustrated through the implementation of an MPEG4 video encoder for QCIF and CIF formats. The experiments show clearly how DMS can be adapted to accommodate different SoC configurations requiring various data transfer bandwidths. Synthesis results show that bandwidth can scale up to 28.8 GB/sec.

We describe the design of an nRERL microprocessor for ultra-low-energy applications. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit using only nMOS transistors, which can be operated at the leakage-current level [1]. We focus on two main issues; first, the design of a full adiabatic microprocessor, which uses only adiabatic components for all the functional blocks, second, the energy consumption of the nRERL microprocessor including its clocked power generator (CPG). With the experimental results, the nRERL microprocessor consumed 26.22 pJ at 440 kHz.

This paper presents two bus coding schemes for power optimization of application-specific systems: partial pus-invert coding and its extension to multiway partial bus-invert coding. In the first scheme, only a selected subgroup of bus lines is encoded to avoid unnecessary inversion of relatively inactive and/or uncorrelated bus lines which are not included in the subgroup. In the extended scheme, we partition a bus into multiple subbuses by clustering highly correlated bus lines and then encode each subbus independently. We describe a heuristic algorithm of partitioning a bus into subbuses for each encoding scheme. Experimental results for various examples indicate that both encoding schemes are highly efficient for application-specific systems.

The test chip was fabricated with the help of IDEC program of KAIST, Taejon, Korea. This paper was sup- ported by NON DIRECTED RESEARCH FUND, Korea Research Foundation,throught Inter-university Semicon- ductor Research Center, Seoul National University, Seoul, Korea, from 1996 to 1999.

In this paper, we propose an adiabatic register file for ultra-low-energy applications, which uses a new reversible adiabatic logic, nRERL [1]. The nRERL register file discards garbage information with minimal energy dissipation. We designed a 16x8b three-port nRERL register file. From SPICE simulations, we found that the nRERL register file consumes less than 10% of the energy consumed in the conventional register file at the frequency of lower than 1MHz. We also describe how to design a RAM, a large array of the storage cells

Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, CG, effit is shown that the power and delay of CMOS digital circuit can be estimated accurately. CG, effis a strong function of VTH/VDDand VTH/VDDtends to increase in low-voltage region. Hence, the effective capacitance (relative to oxide capacitance, CG, eff, is decreasing in low-voltage low-power designs. Therefore, considering CG, effin accurate power and delay) estimation becomes more important in the future.

We presen t a partial bus-in vertcoding scheme for po wer optim ization of system level bus. In the proposed sch eme, we select a su b-group of bus lines involved in b us encoding to a void unnecessary inversion of b us lines not in the sub-group thereby redu cing th e total number of bus transitions. We propose a heuristic algorithm that selects the sub-grou p of bus lines for b us encoding. Ex periments on benchmark examples in dicate that the partial bus-in vert coding reduces the tot al bus tran sitions b y 62.6% on the av erage, compared to that of the unencoded patterns.

We propose a method of designing a reduced complexity nearest-neighbor classifier with near-minimal computational complexity from a given nearest-neighbor classifier that has high input dimensionality and a large number of class vectors. We applied our method to the classification problem of handwritten numerals in the NIST database. If the complexity of the RCNN classifier is normalized to that of the given classifier, the complexity of the derived classifier is 62 percent, 2 percent higher than that of the optimal classifier. This was found using the exhaustive search.

This paper describes a new motion estimation algorithm that is suitable for hardware implementation and substantially reduces the hardware cost by using a low bit-resolution image in the block matching. In the low bit-resolution image generation, adaptive quantization is employed to reduce the bit resolution of the pixel values, which is better than simple truncation of the least significant bits in preserving the dynamic range of the pixel values. The proposed algorithm consists of two search steps: in the low-resolution search, a set of candidate motion vectors is determined, and in the full-resolution search, the motion vector is found from these candidate motion vectors. The hardware cost of the proposed algorithm is 1/17 times of the full search algorithm, while its peak signal-to-noise ratio is better than that of the 4:1 alternate subsampling for the search range of /spl plusmn/32/spl times//spl plusmn/32. A VLSI architecture of the proposed algorithm is also described, which can concurrently perform two prediction modes of the MPEG2 video standard with the search range of (-32.0,-32.0)-(+31.5,+31.5). We fabricated a MPEG2 motion estimator with a 0.5-/spl mu/m triple-metal CMOS technology. The VLSI chip includes 110 K gates of random logic and 90 K bits of SRAM in a die size of 11.5 mm/spl times/12.5 mm. The full functionality of the fabricated chip was confirmed with an MPEG2 encoder chip.

This paper proposes a weighted hidden control neural network (WHCNN) which incorporates a state weighting function into the conventional HCNN. The state weighting function is trained by the generalized probabilistic descent (GPD) method. The GPD method allows minimization of the number of recognition errors directly, and thus allows approximation of the minimum-error-rate recognizer. As a result, we can find that state prediction residuals from each state contain rich discrimination information. Experimental results on the Korean digit recognition have shown 25% and about 16.7% reduction in the number of recognition errors for closed and open test, respectively. The derived algorithm may be easily applied to other predictive neural networks.

Vector quantization (VQ) is a widely used data compression technique which exploits the correlation of the neighbouring samples. To overcome the high computational complexity problem, several fast vector quantization (FVQ) algorithms have been proposed with the quality of the reconstructed images preserved. The efficiency of an FVQ using triangular inequality elimination (TIE) greatly depends on the selection of an initial code vector in searching for the optimal code vector. We propose a TIE-based FVQ using multiple sorted index tables with respect to the anchor points. In the proposed FVQ, the search region does not depend on the initial code vector. Instead of reducing the search region in the conventional TIE-based methods, this approach is to incrementally extend the search region from the center position in the triangular inequalities. The search region is found in a presorted, augmented codebook. We found that the computational complexity of the proposed FVQ is lower than that of Li's (see LEEE Trans. CAS for Video Technology, vol.5, no.2, p.119-123, 1995) FVQ.

We propose a new motion estimation algorithm using low-resolution quantization. The proposed algorithm reduces both performance degradation and computational cost by matching at every search position with a low bit resolution image. It consists of two steps: the low resolution search that generates the candidate motion vectors and the full-resolution search that finds the best motion vector in the candidates from the low-resolution search. Simulation results show that the PSNR of the proposed algorithm is superior to that of the 4:1 alternate subsampling algorithm and the one-dimensional full search algorithm with less computational cost. The PSNR degradation of the proposed algorithm with respect to the full search algorithm is less than 0.12 dB with 1/17.7 computational cost.

A very high precision is needed to implement the adder using stochastic computation (or pulse arithmetic) in modern VLSI technology. In this paper we propose a new model of perceptron using random bitstreams that alleviates this problem.

For many real applications of pattern classification problems, it is more important to reduce the misclassification rate than to increase the rate of successful classification. In this paper, we propose a single-layer neural network with two rejection mechanisms for character recognition problems, which guarantees a very low misclassification rate. The proposed architecture is a cascaded connection of an SLP network and a simple combinational circuit. Comparing to the MLP network, it yields fast learning and requires a simple hardware architecture. We also introduce a new linearly separable coding scheme for training the SLP network to reduce the misclassification rate. We prepared two databases: one with 135,000 digit patterns and the other with 117,000 letter patterns. Then we applied the proposed method to the classification problem for the databases and results show that the misclassification rate is significantly low with maintaining a high recognition rate.>

Stochastic computation uses pulse streams to represent numbers. In this paper, we have studied the novel method to implement the number system which uses the ratio of the number of one (high) pulses and the number of zero (low) pulses in a pulse stream. With this number system, if we let P be the probability that the pulse is one in a pulse stream, then the number Y we want to deal with is defined as Y=P/(1-P). We have studied the method to implement the basic operations such as an addition, a multiplication and a division using this number system and considered the error characteristics of such operations in stochastic computation. Also we introduce an averaging circuit to reduce the error which is inherent in stochastic computation. According to the study, by using this number system we can implement artificial neural networks and represent the simulation results for the digit recognition problem.>

In this paper, we propose a new approach of solving the stereopsis problem with a discrete-time cellular neural network (DTCNN) where each node has connections only with its local neighbors. Because the matching process of stereo correspondence depends on its geometrically local characteristics, the DTCNN is suitable for the stereo correspondence. Moreover, it can be easily implemented in VLSI. Therefore, we employed a two-layer DTCNN with dual templates, which are determined with the back propagation learning rule. Based on evaluation of the proposed approach for several random dot stereograms, its performance is better than that of the Marr-Poggio algorithm.>