Traditional curricular structures can be fragmented in the sense that course inter-relationships or links between theories, methodologies, and practices, are not immediately recognized by the students. The completion of the course puzzle and the integration of course knowledge usually become evident only after graduation. In this paper, we describe a course/lab implementation that has offered students a unique opportunity to experience the full spectrum of course elements, namely, fundamentals of theory, algorithmic design, hardware design and simulation, and implementation and testing on programmable logic devices all within a single framework. The course/lab design has been a collaborative effort between the Dept. of Electrical Engr. (EE) at the University of New Orleans (UNO) and the Dept. of Math and Computer Science (CS) at Barry University (BU). This has helped ensure that the course/ lab offerings can be implemented successfully in diverse environments.

Field-programmable interconnection chips (FPIC's) provide the capability of realizing user programmable interconnection for any desired permutation. Such an interconnection is very much desired for supporting rapid prototyping of hardware systems and for providing programmable communication networks for parallel and distributed computing. An FPIC should realize any possible permutation of input to output pins via a set of programmable switches. In this paper, we show that any such architecture requires a minimum of /spl Omega/(n log n) switches, where /spl Omega/ is the number of I/O pins. The result stems from an analysis of the underlying permutation network. In addition, for networks of bounded degree d, we prove an /spl Omega/(log/sub d-1/ n) bound on the routing delay (maximum length of routing paths for specific I/O permutations) and an /spl Omega/(n log/sub d-1/ n) bound on the average utilization of programmable switches used by the FPIC to implement a specific permutation. For the same type of networks, we prove an /spl Omega/(n log/sub d-1/ n) bound on the number of nodes of the network. Furthermore, we design efficient architectures for FPIC's offering a wide variety of routing delays, high average programmable resource utilization, and O(n/sup 2/)-area two-layer layouts. The proposed structures are called hybrid Benes-Crossbar (HBC) architectures and clearly exhibit a tradeoff between performance (routing delay utilization) and area of the layout.

This paper presents the problem of drawing a graph in the plane so that edges appear as straight lines and the minimum angle formed by any pair of incident edges is maximized. The resolution of a layout is defined to be the size of the minimum angle formed by incident edges of the graph, and the resolution of a graph to be the maximum resolution of any layout of the graph. The resolution R of a graph is characterized in terms of the maximum node degree d of the graph by proving that $\Omega (\frac{1}{{d^2 }}) \leqslant R \leqslant \frac{{2\pi }}{d}$ for any graph. Moreover, it is proved that $R = \Theta (\frac{1}{d})$ for many graphs including planar graphs, complete graphs, hypercubes, multidimensional meshes and tori, and other special networks. It is also shown that the problem of deciding if $R = \frac{{2\pi }}{d}$ for a graph is NP-hard for $d = 4$, and by using a counting argument that $R = O(\frac{{\log d}}{{d^2 }})$ for many graphs.

The problem of drawing a graph in the plane so that edges appear as straight lines and the minimum angle formed by any pair of incident edges is maximized is studied. The resolution of a layout is defined to be the size of the minimum angle formed by incident edges of the graph, and the resolution of a graph is defined to be the maximum resolution of any layout of the graph. The resolution R of a graph is characterized in terms of the maximum node degree d of the graph by proving that Omega (1/d/sup 2/)>