The exponential growth in data center traffic driven by Cloud computing and Artificial Intelligence (AI) has created an urgent need for innovative solutions to achieve energy-efficient computing and communication. Silicon photonics (SiP), a promising technology for next-generation integrated circuits, has already demonstrated its potential in enabling high-capacity optical interconnects. Beyond data centers, SiP offers transformative possibilities in domains such as optical signal processing and high-speed parallel computation for AI workloads. This tutorial review aims to provide electronic IC designers with an introduction to silicon photonic devices, circuits, and CMOS-photonic integration. This tutorial covers the fundamentals of SiP devices, their compact modeling, and interface with CMOS circuits. Additionally, an overview of emerging use cases of EPICs beyond optical interconnects is included.

Recent Germanium electro-absorption modulators (EAM) integrated into silicon photonic platforms promise energy-efficient electrooptic modulation. The Franz Keldysh absorption effect with a sub-ps response enables their high-speed modulation. Furthermore, the compact EAM footprint with a small capacitive load allows a lumped CMOS-based driver. However, the resulting large photocurrent due to absorption in EAM poses a challenge at moderate to high transmitter (TX) laser power, which hasn’t been adequately addressed in the prior art. This work demonstrates a novel push-pull 2.4VppNRZ CMOS driver at 32 Gb/s speed. The driver features a segmented design with a tunable class-AB style stage to source/sink the large photocurrent. The driver is designed in the 65nm LP CMOS technology operating with dual supply voltages of 2.4V and 1.2V, offering seamless operation from 0dBm to 17dBm TX laser power with energy efficiency of 0.7-0.8 pJ/bit for nominal TX laser power settings (0-8dBm) and achieving an extinction ratio (ER) of 4.14dB. The compact layout only occupies 9736µm2area.

Silicon photonics has emerged as a key enabler for progressing integrated circuits in the post-Moore scaling era, whereby the advantages of photonics complement the mature and robust CMOS circuit. The hybrid integration of CMOS electronics and photonics realizes entirely novel system-level functionality. Photonic integrated circuits (PICs) extensively employ thermo-optic tuning for calibrating for process and temperature variations, and also for reconfiguration of these circuits. These thermo-optic phase-shifters, or microheaters, are driven by electronic digital-to-analog converters (DACs) which induce an optical phase-shift proportional to the power delivered. Thus, linear power sweeping capability is desired from the DAC. In this work, we introduce power linear DACs, or PLDACs, which are expected to become a pervasive block in hybrid CMOS-photonic circuits. The mostly-digital PLDAC designed in the TSMC 65nm LP CMOS technology comprises of a 4-bit$\Delta \Sigma$modulator followed by a 4-bit current-steering DAC, a square root circuit, and the driver. The 12-bit PLDAC operates at an oversampled clock rate of 10MHz and delivers up to 24mW of power to doped-silicon microheaters in a SiP foundry process with an estimated silicon footprint of$305\mu \mathrm{m}\times 66\mu \mathrm{m}$.

Spiking Neural Networks shows promising results as the architecture of choice for realizing neuromorphic circuits based on emerging nonvolatile memory devices. High classification performance of Convolutional Neural Networks (CNNs) in processing of unstructured visual data render Spiking Convolutional Neural Networks (SCNNs) as the preferred architecture for energy-efficient visual data processing on neuromorphic system-on-a-chip. Mapping of CNN operation to CMOS/RRAM arrays has recently gained attention but the prior proposed architectures/circuits have been realized with incomplete functionality and peripheral circuit considerations. Max-Pooling is an essential operation in an SCNN layer, but it incurs significant area overhead when implemented directly in RRAM/CMOS. In this work, we propose a novel area-efficient SCNN circuit with temporal Max-Pooling and integrator sharing across the input features. Transistor-level simulations of the proposed SCNN realized on a crossbar array with peripheral circuits are presented using a hybrid 130nm CMOS technology with BEOL integrated HfOxRRAM devices.

Microring modulators integrated in silicon photonic technology platform have evolved to offer much higher energy-efficiency than the conventional Mach Zehnder modulators. This allows for lower drive voltages in the transmitter and compact layout footprint. However, the nonlinear response of the depletion-mode resonant device incurs unequal optical rise and fall times. In this work, we present a transmitter design for a microring based optical interconnects that provides a $1.7 V_{pp}$ swing while avoiding AC-coupling. The direct-coupled driver realized a universal NRZ transmitter with a small footprint. The transmitter is designed in a 65nm LP CMOS technology with 1.2V supply voltage and achieves 1.85 pJ/bit energy-efficiency at 25Gbps data rate, $\gt 8$ dB extinction ratio and 0.075mm2area.

Hybrid integration of the resistive Random Access Memory (RRAM) arrays with standard CMOS has gained recent attention for realization of neuromorphic computing hardware. Such architectures are expected to result in orders of magnitude higher energy-efficiency than their digital counterparts. While a few fully-connected neural networks have been realized using RRAM arrays, a parallel hardware implementation of convolutional neural networks (CNNs) has lagged due to the sequential nature of processing. Prominent reasons include high device variability, lower yield of fabricated 1T1R RRAM devices, and the challenges associated with the retention of multi-levels states in RRAM synapses due to their resistance drift. In this work, we propose and analyze a hybrid solution where constant-gmCMOS-RRAM cells hold the kernel weights and CMOS mirrors are used for Spiking Neural Network (SNN) processing. This is in contrast with the approaches where all weights are implemented using individual 1T1R cells, or addressing is used to route spikes to an SNN that only implements the CNN kernel.

Emerging nonvolatile memory (NVM) devices are being intensely researched to realize energy-sustainable hardware for Edge-Artificial Intelligence applications. Mixed-Signal neuromorphic computing paradigm aims to leverage these NVMs to perform artificial neural network (ANN) computations inside high-density memory arrays in analog domain resulting in significant energy efficiency gain over digital realizations. While the challenges of variability, resolution, retention, and endurance of RRAM devices are being addressed, only meagre attention has been paid to the active neuron circuits that drive the memory arrays. While a CMOS neuron needs to drive a large fan-out of resistive devices with very low quiescent current, CMOS process variability can affect the overall neural network performance. In this work, the effects of process-induced variations are analyzed for RRAM-compatible CMOS neurons and a novel design is presented to mitigate these effects and allow low-power inference.

Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface need immediate attention from the community. In this work, we perform energy-estimation of a NeuSoC system and predict the desirable circuit and device parameters for energy-efficiency optimization. Also, CMOS synapse circuits based on the concept of CMOS memristor emulator are presented as a system prototyping methodology, while practical memristor devices are being developed and integrated with general-purpose CMOS. The proposed mixed-signal memristive synapse can be designed and fabricated using standard CMOS technologies and open doors to interesting applications in cognitive computing circuits.

Large-scale integration of emerging nanoscale non-volatile memory devices, e.g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems. Such hybrid CMOS-RRAM neuromorphic architectures will result in several orders of magnitude reduction in energy consumption at a very small form factor, and herald autonomous learning machines capable of self-adapting to their environment. However, the progress in this area has been impeded from the realization that the actual memory devices fall well short of their expected behavior. In this work, we discuss the challenges associated with these memory devices and their use in neuromorphic computing circuits, and propose pathways to overcome these limitations by introducing `dendritic learning'.

A systematic design method is applied to perform the loop stability and noise analyses for a type-II 3rd-order charge pump PLL. The measured phase noise has shown that the phase noise breakdown simulation can accurately evaluate the PLL performance. The designed PLL outputs a clock at more than 10 GHz for an on-chip SerDes system. The design consideration and trade-off are detailed. The PLL is designed in the IBM 130 nm SiGe BiCMOS process and demonstrated with a prototype PCB for an optical transmitter. When input with an 83 MHz reference clock from a high quality signal generator, the measured PLL/64 output (166 MHz) has a phase noise of -109.3 dBc/Hz and -131.1 dBc/Hz at 100 Hz and 1 MHz offset frequencies, respectively. The PLL output (10.624 GHz) phase noise is converted to have 0.81 ps rms jitter. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy-inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigurable architecture with a single opamp, the described neuron accommodates a large number of memristor synapses, and enables online spike timing dependent plasticity (STDP) learning with optimized power consumption. Simulation results of an 180nm CMOS design showed 97% power efficiency metric when realizing STDP learning in 10,000 memristor synapses with a nominal 1MΩ memristance, and only 13μA current consumption when integrating input spikes. Therefore, the described CMOS neuron contributes a generalized building block for large-scale brain-inspired neuromorphic systems.