The synthesis of VHDL procedures and functions is studied from the VHDL transformation point of view. Among all the proposed methods, inline expansion and modules can be integrated into a VHDL synthesis system by a source-to-source transformation, while a control-subroutine approach requires additional work at the higher-level synthesis phases before it can be linked to a logic synthesis tool. The possibility of carrying out a lot of optimization is explored during the process. We also present various generations of the control-subroutine approach, including the synthesis of recursive programs, a behavioral partitioning methodology that divides the controller into several communicating state machines, and a methodology that mixes the execution of subprograms. Our study shows that the combination of these approaches is flexible enough to be adapted to various applications in an efficient way.

Evaluation of design cost and performance is indispensable to system partitioning. In the absence of a system-level estimation and analysis tool, system partitioning is difficult to perform in an efficient and accurate manner because design evaluation can only be done after the final results are achieved. Furthermore, without cost-performance tradeoff information relating to different design alternatives, the designer can not make intelligent design decisions at the early system-level partitioning stages. In this paper, we present a system-level cost/performance evaluation approach which systematically explores the AT (Area-Time) design-space from a system description. This allows the designer to obtain first-hand design tradeoff information before the partitioning process has taken place. We have also developed a system-level interactive design evaluation system on top of the proposed approach. Experiments on a number of examples demonstrate that our approach provides the designer with a comprehensive system-level design evaluation method to effectively explore all possible design, alternatives in the early stages of system development.

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.

A technique for the resource constrained scheduling problem in high level synthesis is presented. The approach works by successively partitioning the control steps into zones and solving each of them by a 0.1 integer linear programming (ILP) technique. By specifying the maximum, number of 0-1 variables involved within a zone, the model can be turned into optimal ILP scheduling, list scheduling, or something in between with different speed/quality characteristics. Experiments show that better results than those achieved by list scheduling have been obtained with an acceptable computation overhead.>

The authors point out that pipelining is an effective method for optimizing the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. Although throughput and turnaround time are two important optimization criteria, previous work emphasized mainly the throughput. It is shown that the delay time for executing an iteration of a loop has a strong relationship to the cost of the registers and the controller. By minimizing the delay, there is more silicon area to allocate to additional resources, which in turn increases throughput. Forward scheduling and a backward scheduling are iteratively used to achieve this purpose. The algorithm, called PipeLining Scheduler or PLS, can be used to pipeline a loop with or without loop-carried dependencies. Real examples are used to illustrate the method. Experiments on benchmark examples show that considerable improvement over previous approaches is attained.>

We present an algorithm for pipelining loop execution in the presence of loop catried dependence.We optimize both the initiation interval and the turn around time of a schedule.Given constraints on the number of functional units and buses, we tirst determine an initiation interval and then incrementally partition the operations into blocks to fit into the execution windows.A refinement procedure is inwrporated to improve the turn around time.The novel feature which differs our approach from others is that the scheduled operations me iteratively moved up and down to accommodate the ready yet unscheduled opera-tio~.The algorithm produces very encourageous results.

The authors present a controller synthesizer for application-specific multi-function-unit processors. They describe the data path, control path, and timing scheme of the design. They discuss the optimization problems for this architecture, including the translation of a controller-independent schedule into a microprogram to fit the timing scheme and the address assignment of micro-words. They verify the designs using a function simulator and a timing simulator. The synthesized results are proved to be correct by simulation, and a design with 22 ns for each phase, which corresponds to 23 MHz, has been obtained.>

An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining, multicycle operations by nonpipelined function units, and multicycle operations by pipelined function units; functional pipelining; loop folding; mutually exclusive operations; scheduling under bus constraint; and minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O(s*n) where s and n are the number of control steps and operations, respectively. Since the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques are used to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds.>

This paper presents an integer linear programming model for the scheduling problem in high level synthesis under resource constraints. Extensive consideration is given to the following applications: