SUMMARY: pyCapsid is a Python package developed to facilitate the characterization of the dynamics and quasi-rigid mechanical units of protein shells and other protein complexes. The package was developed in response to the rapid increase of high-resolution structures, particularly capsids of viruses, requiring multiscale biophysical analyses. Given a protein shell, pyCapsid generates the collective vibrations of its amino-acid residues, identifies quasi-rigid mechanical regions associated with the disassembly of the structure, and maps the results back to the input proteins for interpretation. pyCapsid summarizes the main results in a report that includes publication-quality figures. AVAILABILITY AND IMPLEMENTATION: pyCapsid's source code is available under MIT License on GitHub. It is compatible with Python 3.8-3.10 and has been deployed in two leading Python package-management systems, PIP and Conda. Installation instructions and tutorials are available in the online documentation and in the pyCapsid's YouTube playlist. In addition, a cloud-based implementation of pyCapsid is available as a Google Colab notebook. pyCapsid Colab does not require installation and generates the same report and outputs as the installable version. Users can post issues regarding pyCapsid in the repository's issues section.

A multichannel portable instrument for on-chip optical absorption spectroscopy is presented. The system can house photonic chips having up to 6 sensing sites operating in parallel, allowing real-time simultaneous detection of multiple chemicals. A 6-channel CMOS lock-in front-end performs the amplification and demodulation of the signals from the integrated light detectors, while an FPGA is chosen for signal acquisition and analysis. A digital real-time ratiometric processing cancels out the effect of laser power fluctuations to achieve high sensitivity in monitoring the presence of the analytes, as demonstrated with the detection of an acetone sample. Compact size for portability, real-time parallel detection and flexible FPGA processing make this system suitable for environmental investigations on many different pollutants, both in the near- and mid-infrared wavelength range.

We propose an accuracy driven synthesis methodology for analog circuits. The proposed approach relies on macro-models for performance estimation and is thus orders of magnitude faster than simulation based synthesis techniques. Unlike existing macro-model based approaches, which use static models, our approach dynamically improves the accuracy of the model during synthesis to ensure true convergence. Our method is based on identifying and accurately modeling those regions in the design space where feasible designs lie. The identified feasible regions and their corresponding models are used in conjunction with an initially generated global model for performance estimation. Experimental results demonstrate that the proposed approach is able to synthesize designs using the enhanced performance models quickly, yet accurately.

Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.

We propose a methodology for sizing radio-frequency circuits. Techniques for including layout information during circuit sizing have been presented. The aim of the proposed technique is to obtain parasitic closure at the post-layout validation stage. A two-step approach is adopted for achieving this goal. In the first step, the interconnect parasitic bounds are estimated. In the second step, the parasitic bounds are used to identify the worst case parasitics and the circuit is resized in presence of these parasitics. The proposed approach unlike existing layout-inclusive approaches achieves parasitic closure while not restricting the flexibility and quality of the physical layout. This methodology was applied on RF circuits like low noise amplifiers and the results demonstrate that our technique helps in obtaining robust parasitic aware design solutions.

Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow. A layout aware methodology for synthesis of analog CMOS circuits using these parasitic models is presented. Results indicate that the proposed synthesis system is fast as compared to a layout-inclusive synthesis approach.

This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called element coefficient diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.

This paper presents a high-level language MSL, for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. In contrast to traditional post-layout extraction, this is done without ever generating a layout. We call this pre-layout extraction. Pre-layout extraction is much faster than post-layout extraction and is highly suited for use in layout-aware circuit sizing programs. MSL can also be used for the specification of parameterized layout generators. Thus, although a concrete layout is never generated during pre-extraction, the extracted circuit is very much influenced by the symbolic placement and routing specified in the layout generation part of the MSL program. This ensures that the pre-layout extraction process yields the same results as post-layout extraction. Being a high-level language based approach, users can tune pre-layout extraction to a desired level of accuracy by modeling selected parasitics and ignoring others. This ability helps further speed up the circuit sizing process up to a factor varying from 2.5 to 4.5 compared to layout-inclusive synthesis methodologies.