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Gavriela Freund Lev

dblp:82/848 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1981
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 50% Electronic design automation · 25% Parallel and multicore computing · 25%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel algorithms
0.011981
A Fast Parallel Algorithm for Routing in Permutation Networks · IEEE Trans. Computers 1981
Interconnection networks and networks-on-chip › routing algorithms
parallel routing
0.011981
A Fast Parallel Algorithm for Routing in Permutation Networks · IEEE Trans. Computers 1981
Interconnection networks and networks-on-chip › routing algorithms
permutation routing
0.011981
A Fast Parallel Algorithm for Routing in Permutation Networks · IEEE Trans. Computers 1981
Electronic design automation › physical design
routing
0.011981
A Fast Parallel Algorithm for Routing in Permutation Networks · IEEE Trans. Computers 1981
Algorithms and data structures
parallel algorithms
0.011981
A Fast Parallel Algorithm for Routing in Permutation Networks · IEEE Trans. Computers 1981

Methods — techniques the papers use, named apart from their topics

parallel algorithm · 0.0
YearPublicationVenuePosition
1981 A Fast Parallel Algorithm for Routing in Permutation Networks
abstract
An algorithm is given for routing in permutation networks-that is, for computing the switch settings that implement a given permutation. The algorithm takes serial timeO(n(logN)2) (for one processor with random access to a memory ofO(n) words) or parallel timeO((logn)3) (fornsynchronous processors with conflict-free random access to a common memory ofO(n) words). These time bounds may be reduced by a further logarithmic factor when all of the switch sizes are integral powers of two.
Gavriela Freund Lev, Nicholas Pippenger, Leslie G. Valiant
IEEE Trans. Computers1