This paper presents a discontinuous conduction mode (DCM) hysteretic buck converter for battery-powered Internet of Things (IoT) sensors. To reduce the quiescent power consumption, a duty-cycled comparator with delay compensation feedback loop is used in the zero current detector (ZCD). This feedback loop generates a self-calibrated comparator input offset to compensate for the comparator propagation delay. Additionally, a dynamic biasing scheme is applied to the hysteretic comparator to enhance the conversion efficiency under light load. The proposed buck converter was implemented in a 55-nm CMOS BCDLite process with an active area of 0.76mm$ \times 0.69$mm. With 310 nA quiescent current, this buck converter supports load currents in the range of$1~{\mu }$A - 300 mA with output voltage 0.8 V - 2.2 V. In particular, greater than 90% efficiency is maintained for load current from$10~{\mu }$A to 100 mA with 95.8% peak efficiency.

This paper presents a novel class H audio amplifier design that allows full class H operating region, optimizing the efficiency of the class H audio amplifier architecture. Class H audio amplifier is a class AB amplifier, with supply continuously tracks the output voltage, gaining the linearity and power supply rejection ratio (PSRR) performance of the class AB amplifier with much higher efficiency. In prior works on class H audio amplifier architecture, the supply tracking capability has always been limited by the minimum supply requirement for the class AB amplifier to operate. A novel class AB amplifier circuit with bootstrapping architecture to overcome this limitation will be introduced in this paper. The proposed class H audio amplifier is designed and fabricated in GF 55nm BCDLite process, occupying 2.01mm2 total chip area. The proposed class H audio amplifier is able to deliver 186.8mW peak output power to$16\Omega $audio load, while consuming 4.9mW quiescent power. It achieves the lowest A-weighted THD+N of −82dB and −81.5dB at 1kHz and 20kHz, respectively. The proposed class H audio amplifier also achieves 85.1% peak power efficiency, the highest as compared to prior works on class G and class H audio amplifiers. Furthermore, it is also shown in this paper that the efficiency at lower output power is significantly improved with the proposed class H audio amplifier architecture, making it highly suitable for audio applications with high crest factor (peak-to-average power ratio).

In designing a mm-wave ultra-wideband pulse-Doppler radar IC, one of the main challenges encountered is to reduce the high power consumption of the circuitries in the IC. A direct-RF receiver can be used in the radar’s design to reduce the radar’s power consumption. However, a digitizer that can directly digitize mm-wave ultra-wideband radar pulses is needed to implement such a receiver. This work presents the design of such a digitizer, which comprises several multi-pass sub-ADCs that operate together. Each multi-pass sub-ADC works fundamentally like a flash ADC but comprises one comparator only. A test chip containing a 6-bit prototype of the digitizer is fabricated in a 40 nm CMOS technology. The prototype consumes 19.7 mW when operated at 4 GSa/s and can operate with input signal frequencies of up to 64 GHz while achieving a −1.7/−6 dBFSSNDRof 21.1/22.8 dB at 60 GHz (the correspondingFoMis 532/434 fJ/c-s). The digitizer has a relatively high effective parallel-equivalent input impedance at 60 GHz, which, in a radar IC implementation, allows it to be driven with a relatively low power-consuming 60 GHz RF buffer. These are achieved without the digitizer being fabricated in a much more advanced technology node.

This paper presents an improvement on the RF-DC rectifier with the self-bias diode-connected MOS transistors to achieve a wide input power range. The proposed design utilized a dual voltage polarity to bias the rectifying PMOS and NMOS with a positive and negative DC potential respectively. This biasing potential enables the gate of the transistor to be boosted above the output voltage or below the rectifier ground to minimize the leakage current. A proposed 3-stage rectifier design is simulated using a 55nm BCD technology and occupies an area of 0.064 mm2. The post-layout simulation results show a 75.3% power conversion efficiency (PCE) at -7dBm, -22.5dBm sensitivity and an input power range of 21.2dB when operating at the 900MHz input RF frequency with a 100k0 load.

The low voltage low power output-capacitorless (OCL) low dropout regulator (LDO) with embedded voltage reference (EVR) with adjustable and programmable output voltage is proposed in this paper. With the proposed design, the embedded voltage reference (EVR) LDO can provide desired output voltages of 435mV, 500mV, 550mV, and 600mV in single LDO design. The dropout voltage is 60mV for low power consumption. The proposed circuit is implemented and simulated in 55nm CMOS technology. The circuit consumes 30μA of quiescent current and 0.0234mm2chip area. Simulation results show that the line regulation is below 12.5mV/V, load regulation is below 2.6mV/mA and temperature coefficient (TC) is below 59ppm/oC under all different output voltage modes of the LDO. Stability of the proposed design is also verified in simulation. The design also has fast transient recovery time of less than 1.67μs under 100ns rise/fall time load current transient.

A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm2including the on-chip calibration unit in 180 nm CMOS.

A novel ac coupled feedback (ACCF) is proposed to alternatively realize fast transient response while inherently controlling the start-up in-rush current of a dc-dc switching converter. The proposed ACCF is modified from a conventional capacitor multiplier and connected between the outputs of the converter and the transconductance. With this supplemental feedback, the transient response has been significantly improved due to the gain-boosting effect around the compensator's midband. Moreover, the ACCF circuit assists to manage the ramping speed of the output voltage during power-up, thereby eliminating the bulky soft-start circuit. The new controller is very simple to implement and occupies a tiny footprint on-chip. A buck converter with the proposed scheme has been fabricated using the 0.18-μm standard CMOS process with an active silicon area of 0.573 mm2. Measurement results show that the output voltage rises linearly for a soft-start period of 1.05 ms according to the designed slope. Excellent load transient responses are achieved under different load current steps; the output voltage overshoot/undershoot of 60 mV settles down within 10 μs for a load variation from 50 μA to 1 A in 1 μs. Moreover, the proposed converter maintains both excellent load and line regulations of 0.018 mV/mA and 0.0056 mV/mV, respectively.

Accurate edge arbitration between two input edges using arbiters or edge comparators is essential in the operation of various mixed-signal systems. However, unlike voltage comparators, input time hysteresis is difficult to be designed into edge comparators. This paper presents a novel edge comparator that has input time hysteresis effect, allowing it to be more robust against noise and jitter in repeated measurements. This was achieved using the SR latch memory effect, and two additional NMOS connected in a negative feedback manner. The proposed edge comparator was fabricated in a standard 0.18μm/1.8V CMOS technology. Simulation results shows a hysteresis window of 55fs. The SR latch memory effect and the presence of the input time hysteresis effect was verified by chip measurement.

As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is proposed. As compared to prior work, it has its own oscillation source on-chip. Moreover, it has a coarse-fine architecture with a smooth coarse-fine interface that allows it to extend its range easily without incurring large overhead costs. It was synthesized in a standard 65nm/1.2V CMOS technology using a VDD of 0.8 V. It is expected to achieve a resolution of 850fs. Simulation results shows a DNL & INL of 0.27 & 2.94LSB respectively, with a FoM of 136/J/conv. step. At a sampling rate of 125MS/s, it consumes 70.8mWof power.

An active capacitor module is proposed to be implemented as a dynamic compensation capacitor at the output of the operational transconductance amplifier (OTA) to improve the load transient response of a DC-DC converter. To enhance the response speed during transient event, an active compensation capacitor module (ACM) is adopted to instantly reduce the capacitance of the compensation capacitor. Compared to the traditional approaches by increasing the transconductance gm of the OTA which introduce higher power consumption, the proposed ACM is more power efficient and it also occupies seven times smaller footprint than the large passive compensation capacitor in this work. A current-mode buck DC-DC converter with an ACM is implemented in 0.18 μim CMOS process and simulated across different process corners. Post-layout simulation results show an excellent load regulation of 0.008 mV/mA during load current variations from 50 μA to 1 A in 1 μs, and the proposed converter is working excellently under different load current steps. Output overshoot/undershoot voltages of 15 mV/22.8 mV with 5.9 μs/6 μs recovery time and 29.5 mV/47.5 mV with 8.8 μs/7.2 μs recovery time are obtained under 0.5 A load current step and 1 A load current step respectively from the simulation. Compared with the conventional converter without ACM, the output overshoot/undershoot voltage and recovery time are approximately reduced by twice and five times respectively.

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -52 to -55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.

A voltage mode DCM boost converter with a square-root voltage mode (SRVM) controller featuring analogue processing is proposed. The controller utilizes as a key parameter the square-root value of the instantaneous load current to obtain pulse-width modulated (PWM) control signals. As a result, no compensation circuits are needed. The output ripples are 0.42% out of the steady-state output of 3 V according to simulation results. Output overshoots of 3 mV with 4 μs recovery time are observed during step-down load transients between 40 and 0 mA in 100 ns. Correspondingly, output undershoots during step-up load transients are less than 10.8 mV with a recovery time of 8.9 μs. The boost converter can start up from its 0.9-V input autonomously based on a proposed two-phase start-up control scheme. In addition, a novel signal boosting technique is presented to ensure gate driving voltages for MOSFET switches as high as attainable to minimize the conduction losses. At the steady state, the boost converter operates with a fixed 1-MHz switching frequency with a 1 μH inductor and a 10 μF capacitor with the maximum load current of 40 mA.

This paper presents a full active rectifier consisting of GaN devices and a CMOS controller designed for wireless power transmission in high-power consumer devices. An adaptive time delay control circuit is developed to maximize the conduction interval of the GaN switch, which can significantly reduce the power loss caused by the forward voltage imposed by the diode. The proposed control algorithm also eliminates the reverse leakage current of the rectifier, and thus further improves its power transfer efficiency. The controller implemented based on a high-voltage 0.18-μm CMOS process and the power stage consisting of four GaN transistors are assembled on the same printed circuit board (PCB) board. The proposed rectifier provides a maximum output current of 3 A at 5 V, with a 6.78-MHz ac input voltage. Its peak power transfer efficiency is 91.8%.

Hysteretic control is popular for switched-capacitor (SC) dc-dc converters. Conventional hysteretic controllers require either a large output capacitor or high-speed output voltage detection for proper regulation. In this paper, a lower boundary hysteretic control method is proposed which matches the output sampling frequency to the converter switching frequency across the entire load range, hence optimal output voltage ripple can be achieved. The converter responses instantly to step-up load transients that are smaller than six times the initial load current. When larger load transient step occurs, the sampling frequency jumps to its maximum value to recover the output voltage quickly. Small output voltage droop can be achieved while using an output capacitance value on the same order as the converter's charge transferring capacitance. A 1/2 step-down SC dc-dc converter with the proposed control technique is fabricated in 0.18-μm CMOS process. The converter achieves a peak efficiency of 86.4% and delivers a maximum output power of 5 mW.

This paper presents a novel class H power amplifier aiming for audio applications on battery-powered electronic devices. The power supply of the amplifier is adaptively adjusted to track the instantaneous input signal amplitude for higher power efficiency. By embedding audio input signal amplitude information into the class AB amplifier's output common-mode voltage level, the amplifier is able to operate with only single-rail power supply and demonstrates more smooth transitions between the light load and heavy load mode, hence achieves lower total harmonic distortion (THD) for a wide load range. Fabricated in the AMS 0.18-μm CMOS process, the chip consumes 3.52 mW quiescent power and is able to deliver 526 mW peak output power to a 16 Ω load. The measurement results indicate that the amplifier incurs no deterioration on THD when entering the supplytracking mode and achieves a lowest THD+N ratio of -80 dB. The peak power efficiency of the system is 80.4%; moreover, it demonstrates significant higher efficiency for medium load range compared to other linear mode amplifiers.

This paper presents a high linearity time-mode temperature sensor with close-loop architecture. The main loop utilizes a switched-capacitor equivalent resistor (Reqsc) to convert the linear values of ΔVBE and the output period of a Voltage-Controlled-Oscillator (VCO) into the control voltage of the VCO. A temperature independent equivalent resistor (Req) whose value only depends on clock period and capacitor value is built to overcome the PVT variations. When Req is equal to Reqsc, the output periods of the VCO which only contains capacitors' ratio are linear with temperature values. Based on the existence of close loop feedback, the proposed temperature sensor achieves excellent temperature linearity. The gain-enhanced and offset-free integrator is adopted, the design requirements of the VCO and reference clock are significantly relaxed. Within the temperature range of -40 °C to 120 °C, the output periods achieve equivalent temperature error of -0.6 °C/0.5 °C with two-point calibration.

This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in fast conversion and negligible overhead. The weight of each branch could be defined flexibly with certain constraints, which is derived in this brief. Moreover, the nonbinary output codes are encoded to binary codes by adder-based encoding logics that show far less power and area penalty. To demonstrate the proposed nonbinary searching technique, a 10-bit 280-MS/s high-speed SAR-ADC is presented, which achieved an signal-to-noise-distortion ratio of 52.4 dB and a figure of merit of 21 fJ/conversion step.

This brief presents an asymmetrical dead-time control driver (ASDTCD) for synchronous buck converter operating in the continuous conduction mode. Dead-time control is an important metric for improving the efficiency of switching mode power regulator. Without an additional circuit, the proposed ASDTCD can generate dead time by controlling the slope for the output signal of the driver. The proposed ASDTCD utilizes the transition between triode region and saturation region for the power transistor to avoid body-diode conduction and shoot-through current while minimizing the switching loss. Thus, high-speed body-diode conduction sensor is avoided; thereby, reducing the power consumption and saving silicon area. In addition, the body-diode conduction time control accuracy is also enhanced. Less than 1-ns body-diode conduction time has been achieved without bringing in shoot-through current across 10-450-mA load range. With less than 0.5% of the total input power consumed, the proposed ASDTCD takes less than 1% of the power transistor area. This design is implemented in the 0.18-μm CMOS process.

The only loss in the lumped circuit model of a wireless power transfer system comes from the parasitic resistances, which usually becomes more problematic at higher frequencies. Resonant currents and voltages can also exert a large stress on the system. This paper presents a simple coil design procedure that minimizes the AC resistance and the stress of the compensating capacitors. It results in the lightest coil designs that can be chosen from commercially available Litz wires. Test setup using SS-topology achieved 98.6 % coil-to-coil efficiency with 18 cm air-gap and 0.6 kg coils.

In this paper, it introduces a proposed hybrid control system which can simultaneously optimize deadtime and reverse inductor current with both the proposed Switched Capacitor Delay Deadtime Controller (SCD-DTC) and Unbalanced Input Pair Zero Current Detector (UIP-ZCD). Furthermore, the total silicon chip area of the hybrid control system occupies an area of 1.44mm2. The estimated power efficiency is 95.8% which has taken into account of losses due to wire bonding, package leads, PCB traces and other parasitic effects. The VIN_BUCKis 2.8-3.3V and being regulated to a VOUTvalue of 1.8V while driving 5-30mA of load current. The proposed SCD-DTC implemented in the buck converter minimizes the duration of body diode conduction to be <; 0.1ns.

A high resolution Vernier Ring Time-to-digital Converter is presented in this paper. Body bias is applied to its delay cells to obtain a finer delay difference between two delay chains. The delay cells and arbiters are implemented in a ring structure, thus allowing a large input time interval to be measured. The digital circuit nature of this converter is also attractive for low power and small area design. The simulation results reveal a 3 ps resolution, a -0.22/0.11 LSB differential nonlinearity (DNL) and a 9-bit range. The prototype chip is fabricated in 65 nm CMOS process consuming 0.44 mW with a 1.2 V power supply and occupies an area of 0.014 mm2.

A low power, low temperature coefficient and ultra-stable higher order curvature compensated CMOS voltage reference circuit has been designed for use in energy harvesting applications. The circuit can provide a stable reference of 543 mV over a wide supply voltage range from 0.69V to 2.5 V with a line sensitivity of 0.05% / V. The circuit has been designed in 65 nm DTCMOS process. The novelty is the use of a simple higher order curvature correction topology to suppress the reference voltage variation at higher temperatures without any complex circuits. The proposed circuit achieves a temperature coefficient of 2ppm/°C over a wide temperature range of -30°C to +140°C. The power supply rejection ratio is -65 dB from DC to 1kHz and the power consumption at 1V is 60 nW. A calibration methodology is also briefly discussed with optimum results to reduce the reference voltage spread across corners.

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, +0.005/fs].

This paper presents a high efficiency rectifier for inductively power transfer application. The efficiency of the rectifier is optimized by utilizing unbalanced biasing technique in the proposed wide swing cascode comparator controlled switch to suppress the reverse leakage current. The design is implemented in standard CMOS 0.18um AMS process. The targeted application is for telemetry, for use in the ISM band between 125 kHz and 134 kHz. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 94.9% in the frequency range of 125kHz - 2MHz with an AC amplitude ranges from 1.2 V to 2.5V under maximum load current condition. It can source a maximum load current of 55mA and operates well under all process corners conditions.

In this paper, a statistic based time skew calibration method for time-interleaved ADCs is presented. By comparing the mean value of the multiplication of signals in two adjacent channels, the time skew can be estimated. Subsequently, a capacitor array based digitally controlled delay block placed in sampling clock path is adopted to compensate the time skew. In addition, the precision of calibration is further improved through using a monotonic small capacitor array. In a 4-channel 1GS/s 12-bit TI-ADC system, the spurious free dynamic range (SFDR) can be improved to 77.5dB with 0.25ps LSB in the digitally controlled delay block.

Hysteretic control is widely adopted in the power management units (PMUs) for modern electronic devices due to their simple and stable control architecture, as well as the fast load transient response. However, the switching frequency of a traditional hysteretic converter is not fixed. It changes with operating condition and component aging, and hence brings in electro-magnetic interference (EMI) problems and multiphase interleaving difficulties. In this work, a hysteretic buck converter with frequency-locking capability is presented, where the switching frequency is adjusted by tuning the hysteretic window. In addition, the current-mode hysteretic control in this work utilizes a simple feedback network, which consists of only passive components and yet provides significant improvement on output voltage regulation. To achieve good reliability at high temperature and high voltage, the proposed buck converter has been fabricated in a 1μm SOI process with a chip area of 6mm2. Experimental results measured at 1MHz fixed switching frequency with 12V-to-5V voltage conversion and 0.9A load current shows a peak efficiency of 91%.

This brief presents a 10-bits successive approximation register analog-to-digital converter (ADC) with a sampling rate of 1 kS/s for implantable medical devices. This ADC is implemented in a 65-nm CMOS process in which leakage current will be a key design parameter. It imposes the highest degree of simplicity in the design of the ADCs architecture. Thus, the transistor count is minimized, which reduces not only the active power, but also the number of leakage sources. The modified top-plate Vcm-based switching offers energy efficient switching at the capacitive-DAC (CDAC) and uses simple control logic. In addition, the proposed asymmetrical metal-oxide-metal capacitor reduces the size of the CDAC by 90% for a given gain error. Furthermore, the input referred offset voltage of the dynamic comparator can be improved by the top-plate Vcm-based switching method at system level without using any additional transistor. The other building blocks are also simplified for lower power consumption. This ADC occupies an area of 0.046 mm2. At 0.9 V and 1 kS/s, the 10-bits ADC consumes 5.8 nW, in which, 2.34 nW is contributed by leakage power consumption. The ADC achieves 9.1-ENOB and an energy efficiency of 10.94-fJ/conversion step.

This paper proposes a frequency-interleaved ADC (FI-ADC) architecture, which can avoid time skew problem existing in time-interleaved ADC (TI-ADC). The analysis filter bank of the FI-ADC is implemented by low order analog filters and can be integrated easily. In addition, prototype of an 8-channel 2GS/s 12-bit FI-ADC is designed. Based on the spurious-free dynamic range (SFDR), the comparison of variation of analog filter coefficients in FI-ADC and time skew in TI-ADC is done. Simulation results show that FI-ADC is more suitable for GHz implementation, and the proposed FI-ADC has a better gain mismatch tolerance than TI-ADC.

Residue Number System (RNS) offers significant advantages over conventional number system in terms of parallel signal processing and power consumption. This makes it ideally suitable for communication, computer security, digital signal processing, in which long word addition and multiplication are involved critically. However, traditional Analog-Digital (binary)-Residue conversion scheme requires large silicon area and high power consumption. Therefore, direct Analog-to-Residue conversion starts to attract due attention from circuit designers and researchers. This paper describes a new approach to the direct conversion based on clock overlapping technique and the hardware complexity grows only logarithmically with the bit-resolution.

In this paper, an analog current mode implementation of a neuron circuit capable of performing real Gaussian neighborhood taper learning is presented. The neuron cell is compacted with a reusable multiplier that can function as squarer and multiplier for Euclidean and topological distances calculation as well as for Gaussian function characteristics with adjustable learning rate. A four-neuron self-organizing map (SOM) with three dimensional input data is designed and simulated using CSM 0.18 mum technology to demonstrate the learning control and neighborhood adaptation. The network can process 4.55 million vectors per second with a minimum power consumption of 1.6 mW at 1.5 V.

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-mum CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of -103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.

This paper presents a novel systematic offset minimization circuit for designing a class-AB CMOS operational amplifier. The proposed structure has a replica-gain circuit, generating a DC replica bias to the differential input stage, and providing differential gain as well as level conversion to drive the class-AB output stage. Statistical measurements on 15 samples of the amplifier showed the mean and standard deviation of the input offset were of 0.88 mV and 0.49 mV respectively. These results were achieved using an active area of only 3700 /spl mu/m/sup 2/ for the critical differential input stage in a 0.8 /spl mu/m standard CMOS technology.