The paper addresses the issue of how to efficiently incorporate a context free grammar into a large vocabulary speech recognizer while maintaining maximum recognizer performance. The new method uses an evolutional grammar (EG) model which produces finite state machines (FSMs) in real time or "on the fly" to accommodate context free grammatical rules. In addition, word models associated with those grammatical rules are built in real time. By optimizing a recursive transition network (RTN) before recognition, efficient instantaneous expansions of the grammatical rules can be ensured. Since all grammatical information is used at the same time that acoustical decoding is done, as opposed to application during a second "post processing" stage, the best attainable accuracy is ensured. Using these methods one can achieve 98% word accuracy and real-time grammatical decoding on the ARPA Naval Resource Management Task.>

A new architecture is presented to support the general class of real-time large-vocabulary speaker-independent continuous speech recognizers incorporating language models. Many such recognizers require multiple high-performance central processing units (CPU's) as well as high interprocessor communication bandwidth. This array processor provides a peak CPU performance of 2.56 giga-floating point operations per second (GFLOPS) as well as a high-speed communication network. In order to efficiently utilize these resources, algorithms were devised for partitioning speech models for mapping into the array processor. Also, a novel scheme is presented for a functional partitioning of the speech recognizer computations. The recognizer is functionally partitioned into six stages, namely, the linear predictive coding (LPC) based feature extractor, mixture probability computer, (phone) state probability computer, word probability computer, phrase probability computer, and traceback computer. Each of these stages is further subdivided as many times as necessary to fit the individual processing elements (PE's). The functional stages are pipelined and synchronized with the frame rate of the incoming speech signal. This partitioning also allows a multistage stack decoder to be implemented for reduction of computation.>

A linear array processor has been designed and built whose elements consist of a programmable pattern-matching VLSI and a block of local memory. The processor element is called the graph search machine (GSM), and the array processor is called the graph search array (GSA). The array is implemented on PC-compatible plug-in cards, four elements to a card, and currently 16 cards are supported in a parallel arrangement. The instruction rate for the fully configured array is 2.5 GIPS (gigainstructions per second) typical, and 5.6 GIPS peak. The instruction set of the GSM and likewise the GSA is optimized for computing distances and making decisions. These are the two kernel operations of pattern recognition. The GSA was designed primarily for development of connected-word speech recognition applications. To this end, a connected-word recognizer incorporating a single-pass (real-time) finite-state grammar has been developed to run on the array. This implementation is called the single-pass finite-state grammar (SPFSG).>

The Hopfield net algorithm for pattern recognition has been implemented on a single GSM (graph search machine). The authors report on the methods used to implement the algorithm as well as on the algorithm performance as compared with competing architectures. It is shown that the GSM provides a viable alternative architecture for neural net research and development.>

A programmable VLSI processor is described for efficiently computing a variety of kernel operations for speech recognition. These operations include dynamic programming for isolated and connected word recognition using both the template matching approach and the Hidden Markov Model (HMM) approach, dynamic programming for natural language models, and metric computations for vector quantization and distance measurement. As well as being able to efficiently compute a wide class of speech processing operations, the architecture is useful in other areas such as image processing. Working chips have been produced using 1.5 µ CMOS design rules that combine both custom and standard cell approaches.

A programmable VLSI architecture is described for efficiently computing a variety of kernel operations for speech recognition. These operations include dynamic programming for isolated and connected word recognition using both the template matching approach and the Hidden Markov Model (HMM) approach, the use of finite-state grammars (FSG) for connected word recognition, and metric computations for vector quantization and distance measurement. These are collectively referred to as "graph search" operations since a diagram consisting of arcs and nodes is commonly used to illustrate the HMM or FSG. As well as being able to efficiently compute a wide class of speech processing operations, the architecture is useful in other areas such as image processing. A chip design has been completed using 1.75-µm CMOS design rules and combines both custom and standard cell aproaches.