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J. Tellier

dblp:83/10971 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1980
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 88% Performance modeling and evaluation · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault simulation		 0.011980
High-speed concurrent fault simulation with vectors and scalars · DAC 1980
Electronic design automation
hardware verification and test		 0.011980
High-speed concurrent fault simulation with vectors and scalars · DAC 1980
Electronic design automation › hardware verification and test › fault simulation
concurrent fault simulation		 0.011980
High-speed concurrent fault simulation with vectors and scalars · DAC 1980
Performance modeling and evaluation
simulation		 0.011980
High-speed concurrent fault simulation with vectors and scalars · DAC 1980
YearPublicationVenuePosition
1980 High-speed concurrent fault simulation with vectors and scalars
abstract
Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.
Ernst G. Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven
 DAC4