Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptography, digital broadcasting and communication. High- throughput requirements need highly parallel implementations, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Although this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of parallel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined devices usually provide better performance, e.g. in terms of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ethernet standard that achieves on the target architecture up to ~25Gbit/sec throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices.

The application of embedded run-time configurable architectures to System-on-chip design has long been considered a possible major enabling factor, especially in the direction of lowering time-to-market of new products as well as mitigating NRE costs related to verification, bug-fixes and product upgrades. In fact, while achieving significant success in specific application fields, reconfigurable computing has so far mostly failed to reach the high-volume application specific standard products (ASSP) that both in terms of volumes and revenues represent the largest share of today's SoC market. This is essentially due to the area overhead induced by these solutions with respect to standard ASIC design styles, which is unaffordable for the low margins that characterize this specific product class. In this paper, the exploitation of mask-programmable hardware technologies for deploying high volume ASSP is evaluated as a possible mitigation factor to the above discussed issues. The paper provides an introduction to mask-programmable technologies as well as an overview and a classification of most significant available trends and solutions in the field. In particular, the application of mask-level programmability in the context of the most significant trends in reconfigurable architectures is thoroughly discussed. In the authors' opinion it is both useful and necessary to capitalize on and exploit the valuable legacy created by 10 years of exploration of reconfigurable architectures in the context of the new possibilities offered by the emergence of mask-programmable options as a significant factor in SoC design.

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages

The integration of a reconfigurable device into complex SoCs is a common request aimed at adding software programmable efficient computational blocks to a system. In such environment a traditional approach in FPGA design could not meet the need for an easy-to-use and easy-to-integrate device. This paper presents the PiCoGA-II reconfigurable datapath which has been designed as a multi-context array to provide fast dynamic reconfiguration. Architectural choices to reduce the area overhead of this approach are described. A reconfigurable dedicated control unit provides a clear interface for an easy integration of the device together with a hardware support for a programming Mow starting from a sequential high-level language. The logic cells have been redesigned with respect to the previous version, to improve their computational efficiency and flexibility. The PiCoGA-II has been fabricated in 0.13mum CMOS technology. The implementation of several MPEG-2 kernels shows that the multi-context array has a computational density which is 2times higher than an equivalent single-context one and is 2times higher than a Virtex-II FPGA when all the 4 contexts are utilized

In this paper we present the new version of a multi-context reconfigurable datapath called PiCoGA (pipelined configurable gate array). The device provides a clear interface model and can be easily embedded in SoC systems where low power consumption and high computation capability are required. New logic cells and routing architecture have been designed for an efficient implementation of computation-intensive algorithms. The integration of a dedicated control unit for pipeline activity control provides a dataflow computational model which is easy to be integrated in a SoC. The embedded datapath has been designed using a 0.13 /spl mu/m CMOS technology. The implementation of several functions in the datapath achieves an average gate density of 1.3 KGates/mm/sup 2/ for each of the four available contexts.

Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%.

Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. This limitation can be overcome with a DBM (Decoder Based Multicontext) routing architecture which introduces a decoding stage between configuration memories and routing structures, so that the number of SRAM cells can be highly reduced. Both the switch and connect blocks have been designed, at the architectural and schematic level. A suitable router for DBM structures has also been developed. The results show that the approach adopted requires on average only 5% more tracks whereas the device area occupation is reduced up to 40%. We also show that DBM routing architecture does not affect the critical path delay, due to the reduction of the routing wire length.