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Arvind M. Patel

dblp:83/1850 · DBLP profile ↗
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9ranked-venue papers
4as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 3 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
7 papers
Electronic design automation · 96% Processor architecture and microarchitecture · 4%
Theoretical computer science
2 papers
Coding theory · 46% Combinatorics and discrete mathematics · 30% Logic in computer science · 23%

Topics — the 13 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.051985
Hierarchical VLSI Routing - An Approximate Routing Procedure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985
Partitioning for VLSI placement problems · DAC 1981
Placement of variable size circuits on LSI masterslices · DAC 1981
Electronic design automation › physical design
placement
0.031981
Partitioning for VLSI placement problems · DAC 1981
Placement of variable size circuits on LSI masterslices · DAC 1981
The chip layout problem: A placement procedure for lsi · DAC 1977
Electronic design automation › physical design
routing
0.011985
Hierarchical VLSI Routing - An Approximate Routing Procedure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985
Electronic design automation › physical design
circuit partitioning
0.011981
Partitioning for VLSI placement problems · DAC 1981
Electronic design automation › physical design › placement
circuit placement
0.011980
The interchange algorithms for circuit placement problems · DAC 1980
Processor architecture and microarchitecture › memory system microarchitecture
address generation
0.011977
Store Address Generator with On-Line Fault-Detection Capability · IEEE Trans. Computers 1977
Electronic design automation › physical design › placement and routing
gate array layout
0.011985
Hierarchical VLSI Routing - An Approximate Routing Procedure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985
Coding theory › error-correcting codes › block codes
linear code
0.011975
Maximal q -nary linear codes with large minimum distance (Corresp.) · IEEE Trans. Inf. Theory 1975
Logic in computer science
many-valued logic
0.011975
Reed-Muller Like Canonic Forms for Multivalued Functions · IEEE Trans. Computers 1975
Combinatorics and discrete mathematics
switching theory
0.011975
Reed-Muller Like Canonic Forms for Multivalued Functions · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test
fault detection
0.011977
Store Address Generator with On-Line Fault-Detection Capability · IEEE Trans. Computers 1977
Electronic design automation
logic synthesis
0.011975
Reed-Muller Like Canonic Forms for Multivalued Functions · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test › fault diagnosis
online fault detection
0.011977
Store Address Generator with On-Line Fault-Detection Capability · IEEE Trans. Computers 1977

Methods — techniques the papers use, named apart from their topics

hierarchical wiring scheme · 0.0approximate routing procedure · 0.0partitioning algorithm · 0.0matrix method for coefficient determination · 0.0interchange procedure · 0.0pseudorandom address generation · 0.0check bits · 0.0
YearPublicationVenuePosition
1985 Hierarchical VLSI Routing - An Approximate Routing Procedure
abstract
This paper describes an approximate routing procedure. The procedure is quite general and could be applied to both printed circuit boards and integrated circuit chip wiring procedures where a hierarchical wiring scheme is utilized. This procedure has been incorporated in sperry's automatic gate array chip layout system.
Arvind M. Patel, Norman L. Soong, Robert K. Korn
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1981 Placement of variable size circuits on LSI masterslices
K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton
DAC2
1981 Partitioning for VLSI placement problems
Arvind M. Patel, L. C. Cote
DAC1
1980 The interchange algorithms for circuit placement problems
abstract
This paper discusses the applications of interchange procedures to solve circuit placement problems. A theoretical analysis to guage the quality of solutions is presented. Two interchange algorithms (Algo I and Algo II) are programmed and tested for moderate size placement problems. Algo II is an improved version of Algo I. On the basis of the limited computational results. Algo II seems to provide significant improvements without increased computation cost.
L. C. Cote, Arvind M. Patel
DAC2
1980 Computer-aided assignment of manufacturing tolerances
abstract
This paper discusses the problem of assigning manufacturing tolerances in the development of a tolerance chart. A quantitative model is constructed so as to consider both the tolerance capability of the various processes used in the manufacture of a part, as well as the most effective way to combine tolerances in order to establish an overall tolerance. The variations of this model are discussed along with the manual trial and error method. It appears that significant reductions in manufacturing costs can be achieved by applying the automation methods presented in this paper.
Arvind M. Patel
DAC1
1977 The chip layout problem: A placement procedure for lsi
K. H. Khokhani, Arvind M. Patel
DAC2
1977 Store Address Generator with On-Line Fault-Detection Capability
abstract
A novel technique for address generation is presented in this correspondence. This scheme has two useful features. Addresses are generated with check bits as an integral part of the address in order to provide multi-fault-detection capability. To date, there exists no such scheme with this feature. Secondly, the addresses generated through this scheme are pseudorandom; therefore, they can be used for storage hierarchies using hash coding techniques.
Mu Yue Hsiao, Arvind M. Patel, Dhiraj K. Pradhan
IEEE Trans. Computers2
1975 Reed-Muller Like Canonic Forms for Multivalued Functions
abstract
In this correspondence we show the existence of a Reed-Muller like expansion for multivalued functions. We establish that any m-variable, N-valued function [mi]f(xm,xm-1,...x1[/mi]) can be expressed as [mi]Co+ C1x1+ *--+ + CNm_1xmN-1xm-1N-1x1N-1[/mi]. A matrix method for determining the coefficients of these expansions is presented. The problem of finding minimal expression for a given function is discussed. Finally, we present a new technique for realizing multiple output functions.
Dhiraj K. Pradhan, Arvind M. Patel
IEEE Trans. Computers2
1975 Maximal q -nary linear codes with large minimum distance (Corresp.)
abstract
This correspondence presents a complete solution to the problem of constructing maximalq-nary codes, for any word lengthnand minimum distancedin the regionqd \geq (q - 1)n. Several interesting results regarding the interdependence of these codes are developed, which reveal the unique structure of the code spaces of the regionqd \geq (q - 1)n. Some new maximal codes are obtained for the regionqd < (q - 1)n.
Arvind M. Patel
IEEE Trans. Inf. Theory1