This paper introduces an efficient CNN algorithm to address key limitations in Deep Neural Networks (DNNs) used for image recognition, focusing particularly on model size and retraining time. Traditional methods often require significant training durations; however, applying approximation techniques during retraining can exacerbate these time demands. We present an approach that enhances approximation techniques while eliminating the need for model retraining, thus enabling DNN compression with minimal accuracy loss. The proposed method integrates three core strategies: weight arrangement, approximation, and data reuse. The DNN weights are initially arranged in ascending order to optimize subsequent operations. During inference, the approximation is applied to reduce the model size and minimize computational complexity by reducing the number of operations required for each multiply-accumulate (MAC) unit. Then, the original weights are replaced with the approximated values, enabling the reuse of computations and data across different sets of weights. As a result, the method significantly reduces memory access, computational demands, and energy consumption. Experimental results on the CIFAR-10 and TinyImageNet datasets demonstrate that our method achieves a model reduction rate of approximately 198.6× while maintaining a minimal loss in accuracy. The proposed technique bypasses the need for retraining, offering a practical solution to the growing complexity of DNN models in modern applications.

Spiking Neural Networks (SNNs) are emerging as potent alternatives to Convolutional Neural Networks (CNNs), especially for energy-constrained and latency-sensitive applications, due to their spiked activations and inherent sparsity. Rate-coded SNNs, trained with backpropagation through time (BPTT) and using static data over artificial time-steps, have achieved state-of-the-art results on benchmarks like MNIST. For resource-constrained devices, smaller models help meet memory and power limitations. However, shallow rate-coded SNNs often need numerous time-steps for accurate inference, increasing latency and computational cost. To address this, a technique named RTS (Reduced Time-Step) is proposed to reduce time-steps, optimizing the balance between model size and convergence latency. RTSSNN leverages the periodic dynamics of Leaky-Integrate-and-Fire (LIF) neurons’ membrane potentials when stimulated with constant input by adding a small Fully Connected (FC) layer at the end of the network. At this depth, spikes are sparse and stable, allowing reduced time-steps without losing accuracy. Demonstrated on four-bit quantized SNNs on Raspberry Pi, the method achieves 9x, 4x, and 4.9x operations reduction, 3x, 2x, and 2.2x time-step reduction, as well as 2.3x, 1.5x, and 1.9x runtime reduction during inference on MNIST, FashionMNIST, and GTSRB datasets, respectively, with maintained accuracy. It also shows a 4x, 2x, and 1.9x operations, time-step, and runtime reduction in one-bit quantized SNNs. Additional experiments conducted on the higher complexity CIFAR-10 dataset as well as the dynamic neuromorphic N-MNIST dataset confirmed that RTSSNN is effective primarily on shallow networks with static datasets, where stable activations support periodic membrane behavior in LIF neurons.

FALCON is a lattice-based post-quantum cryptographic (PQC) digital signature standard known for its compact signatures and resistance to quantum attacks. Since its recent standardization, its hardware implementation remains an open challenge, particularly for key generation, which is significantly more complex than the simple and well-studied signature verification process. In this paper, targeting edge devices with constrained resources, we present an energy-efficient and area-optimized NTT/INTT architecture tailored to the specific requirements of FALCON key generation. By leveraging NTT-friendly primes and reducing the size of the multipliers in the Montgomery reduction algorithm — optimized for ASIC implementation — our design minimizes hardware complexity, achieving the lowest power and area consumption compared to state-of-the-art Montgomery reduction implementations. The proposed hardware architecture features a processing element array, distributed SRAMs, and ROMs, with three levels of reconfigurability, supporting both NTT and INTT operations. Designed using the Global Foundries’ 22 nm FD-SOI process, an Application-Specific Integrated Circuit (ASIC) is estimated to occupy 0.04 mm 2 and consume 18.2 mW at 1 GHz. The proposed processor achieves 700 times greater energy efficiency and performs computations 200 times faster than software implementations on the ARM Cortex-M4. It also achieves the lowest area–time product and highest energy efficiency among state-of-the-art NTT/INTT hardware accelerators. By carefully balancing power consumption and computational speed, this design offers an efficient solution for deploying FALCON key generation on devices with limited resources.

Extended reality (XR) and 6G networks are set to transform mobile immersive experiences, with privacy and security being paramount in XR communications. Achieving secure and reliable XR experiences while meeting high-resolution and low-latency requirements is challenging for wireless networks. A novel security-aware cross-layer communication management framework is proposed, employing zero-trust spatiotemporal physical layer level manipulations for moving-target defense. Driven by deep reinforcement learning and real-time monitoring, the proposed framework adaptively reprograms the network configuration to maximize the user’s quality of experience (QoE), reduce the overall latency, and minimize the attacker’s intercept probability. The framework was evaluated in a simulated scenario featuring an indirect multi-hop communication setup. The results show that the proposed framework effectively and efficiently secures XR user communications while maintaining QoE, outperforming conventional Q-learning algorithms.

Deep neural networks (DNNs) are indispensable in various artificial intelligence (AI) applications. However, their inherent complexity presents significant challenges, particularly when deploying them on resource-constrained devices. To overcome these hurdles, academia and industry are actively seeking ways to accelerate and optimize DNN implementations. A significant area of research revolves around discovering more effective methods to represent the enormous data volumes processed by DNNs. Traditional number systems (NSs) have proven nonoptimal for this task, prompting extensive exploration into alternative and bespoke systems for DNNs. This survey aims to comprehensively discuss various NSs utilized to efficiently represent DNN data. These systems are categorized mainly based on their impact on DNN performance and hardware implementation. This survey offers an overview of these categorized NSs and delves into different subsystems within each, outlining their effect on DNN performance and hardware design. Furthermore, these systems are compared quantitatively and qualitatively concerning their expected quantization error, memory utilization, and computational requirements. This survey also emphasizes the challenges linked with each system and the diverse proposed solutions to address them. Insights into the utilization of these NSs for sophisticated DNNs are also presented in this survey. Readers will acquire a deeper understanding of the importance of efficient NSs for DNNs, explore commonly used systems, comprehend the tradeoffs between these systems, delve into design considerations influencing their impact on DNN performance, and discover recent trends and potential research avenues in this field.

The Physical Unclonable Function (PUF) is a security mechanism that takes advantage of the physical variations in a device to create a unique response that can be used as a device signature or secure key. However, many DRAM-based PUFs violate the operating rules of commodity DRAM to exploit a source of entropy in the DRAM read path. This work proposes a fast and reliable DRAM-based PUF that evaluates the variation of adjacent cells and produces the response through the normal read operation. The proposed design is implemented using 65-nm technology, and a detailed statistical SPICE simulation verifies its validity. The statistical analysis shows that the proposed PUF achieves 54.19% uniformity and 49.43% uniqueness, with 98% of the investigated responses achieving a Shannon entropy of 0.95. Additionally, the proposed design generates the response by 45, which is at least 66.7 times faster than existing systems. Furthermore, the proposed design uses the relative behavior of cells, which allows for stable responses against temperature and voltage variations, eliminating the need for error correction codes. The proposed PUF also shows resiliency against machine learning-based modeling attacks, as the prediction accuracy does not exceed 55% over 5K Challenge-Response Pairs (CRPs). The area overhead is negligible as the proposed design uses standard circuits, with the addition of only one 2x1 multiplexer at the inputs of the row buffer.

This paper proposes an efficient hardware accelerator named EACNN for use in Convolution Neural Networks. EACNN is an efficient CNN architecture that is based on co-optimization of algorithms and hardware. The proposed approach is based on linear approximation of the weights for pre-trained networks with low loss of accuracy. Furthermore, a weight substitution and remapping technique adopts linear approximation coefficients to replace CNN weights. That leads to a repetition of the weight values across different kernels and enables the reuse of CNN computations for various output feature maps. The input activations corresponding to the same linear co-efficient can be multiplied and accumulated first and then reused to generate multiple output feature maps. This computational reuse method reduces the number of multiplication and addition operations and memory accesses, which is efficiently supported by a dedicated element in the proposed EACNN. Experimental results on CIFAR 10 and CIFAR 100 datasets show that the proposed method eliminates around 61% of the multiplications in the network without significant loss of accuracy$(< 3\%)$. As a demonstration, a hardware accelerator based on EACNN was implemented on Xilinx FPGA Artix 7 and achieved a 50% reduction in the FPGA hardware resources.

Large deep neural network (DNN) models are computation and memory intensive, which limits their deployment especially on edge devices. Therefore, pruning, quantization, data sparsity and data reuse have been applied to DNNs to reduce memory and computation complexity at the expense of some accuracy loss. The reduction in the bit-precision results in loss of information, and the aggressive bit-width reduction could result in noticeable accuracy loss. This paper introduces Scaling-Weight-based Convolution (SWC) technique to reduce the DNN model size and the complexity and number of arithmetic operations. This is achieved by, using a small set of high-precision weights (maximum absolute weight “MAW”) and a large set of low-precision weights (Scaling weights “SWs”). This results in decreasing the model size with minimum loss in accuracy compared to simply reducing the precision. Moreover, a scaling and quantized network-acceleration processor (SQNAP) is proposed based on the SWC method to achieve high-speed and low-power with reduced memory accesses. The proposed SWC eliminate >90% of the multiplications in the network. Moreover, the less important SWs are pruned, which has a small portion of the MAW. Retraining is applied in order to maintain accuracy. Full analysis for MNIST, Fashion MNIST, Cifar 10 and Cifar 100 datasets is presented for image recognition, where different DNN models are used including LeNet, ResNet, AlexNet and VGG 16.

This work introduces a generic, machine learning (ML)-based platform for functional reverse engineering (RE) of circuits. Our proposed platformGNN-REleverages the notion of graph neural networks (GNNs) to: 1) represent and analyze flattened/unstructured gate-level netlists; 2) automatically identify the boundaries between the modules or subcircuits implemented in such netlists; and 3) classify the subcircuits based on their functionalities. For GNNs in general, each graph node is tailored to learn about its own features and its neighboring nodes, which is a powerful approach for the detection of any kind of subgraphs of interest. ForGNN-RE, in particular, each node represents a gate and is initialized with a feature vector that reflects on the functional and structural properties of its neighboring gates.GNN-REalso learns the global structure of the circuit, which facilitates identifying the boundaries between subcircuits in a flattened netlist. Initially, to provide high-quality data for training ofGNN-RE, we deploy a comprehensive dataset of foundational designs/components with differing functionalities, implementation styles, bit widths, and interconnections.GNN-REis then tested on the unseen shares of this custom dataset, as well as the EPFL benchmarks, the ISCAS-85 benchmarks, and the 74X series benchmarks.GNN-REachieves an average accuracy of 98.82% in terms of mapping individual gates to modules, all without any manual intervention or postprocessing. We also release our code and source data.

This paper investigates different precoding strategies for rate splitting multiple access (RSMA) in the downlink of multi-cell visible light communication (VLC) networks. Since classical Shannon capacity formula does not hold for VLC, we first provide a lower bound on the channel capacity for RSMA in such interfering networks. Then, we formulate a spectral efficiency maximization problem to jointly find the optimal rate-splitting and transmit precoding. Beside that, since cell-edge users suffer from additional inter-cell interference, we propose to design the precoders of different RSMA signals utilizing coordinated beamforming (CB). Subsequently, aiming to improve the performance of the CB design for RSMA, while maintain a reduced complexity, we introduce two enhanced precoding strategies for RSMA. To the best of the authors’ knowledge such a contribution has not been considered before in the open literature. It is shown in the paper that the formulated optimization problem is non-convex and a sub-optimal, yet, a low complexity solution can be obtained efficiently using semi-definite relaxation combined with successive convex approximation. Through analytical results, we illustrate the flexibility and superiority of the proposed precoding strategies for RSMA over conventional coordinated space division multiple access and non-orthogonal multiple access for different scenarios and network loads.

Logic locking aims to protect the intellectual property (IP) of integrated circuit (IC) designs throughout the globalized supply chain. The SAIL attack, based on tailored machine learning (ML) models, circumvents combinational logic locking with high accuracy and is amongst the most potent attacks as it does not require a functional IC acting as an oracle. In this work, we propose UNSAIL, a logic locking technique that inserts key-gate structures with the specific aim to confuse ML models like those used in SAIL. More specifically, UNSAIL serves to prevent attacks seeking to resolve the structural transformations of synthesis-induced obfuscation, which is an essential step for logic locking. Our approach is generic; it can protect any local structure of key-gates against such ML-based attacks in an oracle-less setting. We develop a reference implementation for the SAIL attack and launch it on both traditionally locked and UNSAIL-locked designs. For SAIL, two ML models have been proposed (which we implement accordingly), namely a change-prediction model and a reconstruction model; the change-prediction model is used to determine which key-gate structures to restore using the reconstruction model. Our study on benchmarks ranging from the ISCAS-85 and ITC-99 suites to the OpenRISC Reference Platform System-on-Chip (ORPSoC) confirms that UNSAIL degrades the accuracy of the change-prediction model and the reconstruction model by an average of 20.13 and 17 percentage points (pp), respectively. When the aforementioned models are combined, which is the most powerful scenario for SAIL, UNSAIL reduces the attack accuracy of SAIL by an average of 11pp. We further demonstrate that UNSAIL thwarts other oracle-less attacks, i.e., SWEEP and the redundancy attack, indicating the generic nature and strength of our approach. Detailed layout-level evaluations illustrate that UNSAIL incurs minimal area and power overheads of 0.26% and 0.61%, respectively, on the million-gate ORPSoC design.

The electrocardiogram signal (ECG), a record of electrical activity of the cardiac muscle, has been used in diagnosing many cardiopathies. Wearable devices equipped with readout sensors and circuits can be used to record and process weak ECG signals. In this paper, a pre-trained neural network was implemented for detecting the QRS feature of an ECG signal, which is crucial for auto-diagnostic of various cardiopathies. To take advantage of the fast evolution of artificial intelligence and its ability to find non-linear relationships, neural network based feature extraction of ECG signals for wearable devices was explored and tested using ASIC implementation flow. Firstly, a high-level simulation was carried out in MATLAB and verified with test data obtained from PhysioNET database. Recurrent neural network (RNN) MLP was created and trained using the data obtained from PhysioNET database. A high-level performance evaluation was carried out using the same network for P and T wave extraction. The weight and bias matrices obtained from the high-level trained network in MATLAB were used in the design of the hardware. An accuracy of 96.55% was achieved in the hardware implementation of the network.

While financially advantageous, outsourcing key steps such as testing to potentially untrusted Outsourced Semiconductor Assembly and Test (OSAT) companies may pose a risk of compromising on-chip assets. Obfuscation of scan chains is a technique that hides the actual scan data from the untrusted testers; logic inserted between the scan cells, driven by a secret key, hide the transformation functions between the scan-in stimulus (scan-out response) and the delivered scan pattern (captured response). In this paper, we propose ScanSAT: an attack that transforms a scan obfuscated circuit to its logic-locked version and applies a variant of the Boolean satisfiability (SAT) based attack, thereby extracting the secret key. Our empirical results demonstrate that ScanSAT can easily break naive scan obfuscation techniques using only three or fewer attack iterations even for large key sizes and in the presence of scan compression.

Logic locking is a solution that mitigates hardware security threats, such as Trojan insertion, piracy and counterfeiting. Research in this area has led to, in an iterative fashion, a series of logic locking defenses as well as attacks that circumvent these defenses by extracting the logic locking key. The most powerful attacks rely on a full access to a working chip/oracle that can be used to produce the input-output pairs utilized in recovering the secret key. A recently proposed technique Stripped Functionality Logic Locking (SFLL) provides resilience to all known attacks on combinational logic locking. In this paper, we propose a functional reverse engineering attack on SFLL: an attack that can detect the protection logic of SFLL which results in obtaining the original unlocked design with a high success rate. The restore and perturb blocks utilized by SFLL were detected with average coverage percentages of 93.95% and 85.42% respectively, proving that our attack is capable of breaking the state of the art logic locking technique.

The present work investigates the performance of non-orthogonal multiple access (NOMA) in a hybrid visible light communication (VLC) / radio frequency (RF) wireless network. In particular, we investigate the energy efficiency of the proposed architecture assuming imperfect channel state information (CSI), which is a realistic assumption that is encountered in practical indoor and outdoor wireless communication scenarios. We demonstrate that the performance of the proposed scheme in terms of energy efficiency outperforms by four-fold the corresponding performance of its orthogonal frequency division multiple access (OFDMA) counterpart. In addition, it is shown that the energy efficiency of the proposed scheme is more robust to CSI errors and line of sight (LOS) variations than the OFDMA-based scheme, which appears to be more susceptible to the CSI error and the LOS availability probability. Finally, our findings reveal that the performance gain of NOMA over OFDMA in the considered hybrid VLC/RF set up is directly proportional to the probability of LOS availability. These results are expected to be useful in the efficient design and efficient operation of hybrid VLC/RF wireless systems.

Autonomous Mobile agents can be extremely useful in dynamic environments that require a continuous network connection. Network bandwidth reduction, protocol encapsulation, software automation and intelligence gathering can significantly affect Web Services. Integrating mobile agents with Web Services enables software adaptation to cope with a dynamic environment, automated system configuration and application requirement changes that are frequent in today''s ever fast-evolving technology. In this paper, we use a lightweight and efficient composition for mobile agents based Web services complying with Representational State Transfer (REST) principles for agent creation, migration, and control. The paper presents the overall concept and architecture of RESTful agents for web services. A security scheme is proposed for mobile agent security based on an infrastructure-less Identity Based Encryption (IBE) scheme integrated with Broadcast based Secure Mobile Agent Protocol (BROSMAP). A proof- of-concept implementation is provided.

This paper proposes a cluster-based routing pro-tocol for urban Vehicular Ad Hoc Networks (VANETs) using Optimized Link State Routing (OLSR). In OLSR, MultiPoint Relays (MPRs) used for routing, are selected at each node using neighbors' reachability resulting in a high percentage of MPRs. Quality-of-Service (QoS) was introduced to improve MPRs' quality in VANETs while clustering was introduced to reduce MPRs' percentage in dense areas. Relay selection in urban VANETs routing protocols incorporates vehicle mobility metrics, velocity and position whose significance is lowered by abrupt topology change. Our proposed clustering protocol extends the street-centric QoS-OLSR protocol for urban VANETs. QoS and current street are used for cluster head and MPR selection to improve network connectivity, stability, and performance. Simulations conducted using SUMO and NS3 demonstrate that the proposed protocol improves percentage of MPRs, percentage of stability, throughput, packet delivery ratio, hop count and end-to-end delay compared to OLSR and street-centric QoS-OLSR in urban VANET.

Computer vision and recognition is emerging as one of the important pillars in artificial intelligence systems. It is a vital way to interpret the collected data and find matching patterns that will help in real-time decision making. CMOS-based search engines suffer from density and power limitations. Memristor is a feasible candidate that is capable of performing search within a stored structure (in-memory computing). This paper proposes the first memristor-based stateful search engine architecture based on a novel stateful heterogeneous memristive XOR gate. The design is suitable for 2-D media applications, such as image matching and pattern inspection. It performs bitwise comparison using the proposed XOR gate. The output states of all XOR gates are transferred into a single analog memristor value that is read via a digital comparator. The design assumes a single memristor device for each of the incoming data, template, and result bits. Each 2-D array of input, template, and output is reordered into a single 1-D array with 3 × (N × M) structure, where N represents the number of entry data and M is the number of bits per entry. This allows for a significantly higher storage density than conventional CMOSbased or other memristor-based search engines. Simulations of the proposed architecture demonstrate functionalities in search and compare modes using an LTSpice circuit simulator. The proposed architecture achieves a 3-ns search cycle time at 0.34 nJ/database at 1.5 V/1 GHz using 2N + 1 memristors.

Memristor-based hardware accelerators are gaining an increased attention as a potential candidate to speed-up the vector-matrix operations commonly needed in many digital image processing tasks due to their area, speed, and energy efficiency. In this paper, a memristor-based image compression (MR-IC) architecture that exploits a lossy 2-D discrete wavelet transform is proposed. The architecture is composed of a computational memristor crossbar, an intermediate memory array that stores the row-transformed coefficients and a final memory that holds the compressed version of the original image. The computational memristor array performs in-memory computation on the initially stored transformation coefficients. Using the quantitative analysis approach, we demonstrate a 10× reduction in a number of operations compared with a conventional application-specific integrated circuit implementation. This translates to five orders of magnitude reduction in area, around 11× improvement in energy efficiency, and 1.28× speedup in computation time. Image quality metrics, such as peak signal-to-noise ratio (PSNR), structural similarity (SSIM) index, and complex wavelet-SSIM (CW-SSIM), are used to quantify the reduction in image quality due to lossy compression. The achieved metrics for conventional versus MR-IC are: PSNR 57.24 versus 33.29 dB, SSIM 0.9994 versus 0.8853, and CW-SSIM 1 versus 0.9983. Simulation results show that the 32 quantization levels proposed architecture provides significant improvements in energy, area, and performance compared to the 32 levels CMOS implementation with comparable CW-SSIM.

Unipolar RRAM devices are of high interest due to their high resistance ratio and simple selector circuit. In this paper, we report on a measurements from nano-thick memristor featuring a novel Pd/Hf/HfO2/Pd stack. The fabricated device exhibits a unipolar switching behavior, due to the asymmetric device structure and the existence of the Pd metal as a bottom electrode. The forming voltage of the proposed memristive stack (Hf-10nm/HfO2-10nm) is found to be size dependent at the microscale and its average forming voltage decreases by 20% when the active area increases from 30×30 to 1000×1000 μm2. The findings presented in this work highlight the impact of device geometry on its electrical performance and power, which provide guidance to the design tradeoffs (size, power, resistance ratio) and fabrication process of memristor devices.

In this paper, we address the problem of routing in urban Vehicular ad hoc networks (VANETs) using the proactive Optimized Link State Routing (OLSR) protocol. OLSR selects MultiPoint Relays (MPRs) according to neighbors' reachability index while Quality-of-Service OLSR (QoS-OLSR) for highway VANET considers bandwidth, velocity and distance for MPR selection. For urban VANET, several reactive and position-based protocols were proposed using mobility metrics such as velocity and distance. Both QoS-OLSR and urban VANET protocols depend on basic mobility metrics which rapidly change due to environment restrictions; intersections and street topology. Our proposed street-centric QoS-OLSR protocol for urban VANET is considered as the first attempt to use an urban-based QoS metric for OLSR MPR selection. Link and street centric parameters such as bandwidth, street and lane are utilized in the proposed protocol. Simulations are conducted using the modified NS3 OLSR's implementation to incorporate the QoS metric. Simulation results demonstrate that our proposed QoS-OLSR improves throughput, Packet Delivery Ratio (PDR), average hop count and end-to-end delay compared to OLSR in urban VANET.

In this paper, we investigate the application of differential modulation in simultaneous wireless information and power transfer (SWIPT) relay networks. Considering time switching (TS) and power splitting (PS) receiver architectures, we adopt a moments-based approach to derive novel expressions for the outage probability and throughput of SWIPT relay systems with the amplify-and-forward (AF) relaying protocol. We quantify the impact of several system parameters involving the energy conversion efficiency and the TS and PS ratio assumptions, imposed on the energy harvesting (EH) relay terminal. Our results reveal that the throughput performance of the TS protocol is superior to that of the PS protocol at lower receive signal-to-noise (SNR) values, which is in contrast to point-to-point SWIPT systems. A Monte Carlo simulation study is presented to corroborate the proposed analysis.

The rapid increase of connected devices and the major advances in information and communication technologies have led to great emergence in the Internet of Things (IoT). IoT devices require software adaptation as they are in continuous transition. Multi-agent based solutions offer adaptable composition for IoT systems. Mobile agents can also be used to enable interoperability and global intelligence with smart objects in the Internet of Things. The use of agents carrying personal data and the rapid increasing number of connected IoT devices require the use of security protocols to secure the user data. Elliptic Curve Cryptography (ECC) Algorithm has emerged as an attractive and efficient public-key cryptosystem. We recommend the use of ECC in the proposed Broadcast based Secure Mobile Agent Protocol (BROSMAP) which is one of the most secure protocols that provides confidentiality, authentication, authorization, accountability, integrity and non-repudiation. We provide a methodology to improve BROSMAP to fulfill the needs of Multi-agent based IoT Systems in general. The new BROSMAP performs better than its predecessor and provides the same security requirements. We have formally verified ECC-BROSMAP using Scyther and compared it with BROSMAP in terms of execution time and computational cost. The effect of varying the key size on BROSMAP is also presented. A new ECC-based BROSMAP takes half the time of Rivest-Shamir-Adleman (RSA) 2048 BROSMAP and 4 times better than its equivalent RSA 3072 version. The computational cost was found in favor of ECC-BROSMAP which is more efficient by a factor of 561 as compared to the RSA-BROSMAP.

Mobile agents are smart programs that migrate from one platform to another to perform the user task. Mobile agents offer flexibility and performance enhancements to systems and service real-time applications. However, security in mobile agent systems is a great concern. In this paper, we propose a novel Broadcast based Secure Mobile Agent Protocol (BROSMAP) for distributed service applications that provides mutual authentication, authorization, accountability, nonrepudiation, integrity, and confidentiality. The proposed system also provides protection from man in the middle, replay, repudiation, and modification attacks. We proved the efficiency of the proposed protocol through formal verification with Scyther verification tool.

Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin-transfer torque (STT)-RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and low-voltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT-RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT-RAM power has been compared with the traditional six-transistor-SRAM-based memory power and potential application in wireless sensor nodes is explored. This paper uses 45-nm foundry process technology data for SRAM and physics-based mathematical models derived from real devices for memristor and STT-RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT-RAM, respectively, at 1% duty cycle.

In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.

Testing and verification of healthcare information systems is a challenging and important issue since faults in these critical systems may lead to loss of lives, and in the best cases, loss of money and reputations. However, due to the complexity of these systems, and the increasing demand for new products and new technologies in this domain, there are several methods and technologies being used for testing these systems. In this paper, we review the state of the art on testing and verification of healthcare information systems, and then we identify several open issues and challenges in the area. We divide the exiting methods into three categories: simulation based methods, formal methods, and other techniques such as semi-formal methods. Then, we discuss challenging and open issues in the domain.

This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65 nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

This paper presents a new fast and scalable Parallel Union-Find algorithm for image segmentation and its System-on-Chip (SoC) implementation using 65nm CMOS technology following the Application-Specific Integrated Circuit (ASIC) design flow. The algorithm is capable of labeling all foreground and background pixels, using the least possible pixels scanning. This contrasts the classical labeling algorithms that label only foreground (or background) pixels in a single run. The new algorithm utilizes only two memory blocks. In one memory block, it labels image segments using their seeds as the label and, simultaneously, the segments sizes are used as the other label in second memory block. By this parallel labeling, monitoring the image segments is very fast and efficient. With 350 MHz operating frequency, the processing rate estimated to be 2100 frames/sec, the total chip area of 15950.5 μm2 (off-chip memory) and very low-power of 0.3 mW, the SoC tends to be an excellent candidate for mobile devices and real-time applications.

The paper presents a novel technique to segment and extract streets from satellite images. This technique utilizes, for the first time in the known literature, the Maximally Stable Extremal Regions (MSER) algorithm to robustly identify and segment streets from satellite images. The technique extracts dark MSERs and then classifies them based on multiple metrics such as the intensity of the pixels, the region stability, and the major-to-minor axes ratio. Testing results under multiple scenarios corroborate the accuracy of the proposed technique. The technique will allow fast and accurate implementation of a wide spectrum of applications such as in Global Positioning System (GPS) driving guidance.

The increase in demand for higher functionality, smaller size, lower cost and near perpetual operation of Wireless Sensor Nodes (WSNs) are posing big challenges for system designers. A major aspect is the operational lifetime of the system which is determined by the finite energy source supplied by the battery. In WSNs, the higher power incurred due to added system functionality and the increase leakage as a result of technology scaling have high impact on the battery lifetime. In this work, memory was used to further exploit the energy efficiency at the sensor node system-level. A detailed analysis using Semi-Markov model to investigate different operational modes of WSN with the present SRAM shows an improvement of 4x at 90% duty cycle in the node's lifetime. In addition, an emerging non-volatile memory (NVM) technology, Memristor, is also explored to further improve the WSN energy efficiency. Its non-volatility nature will suppress the power wasted as leakage in SRAM during idle periods which is typical for low duty-cycle WSNs. The results show that utilizing an on-chip NVM can further improve WSN lifetime by 1x for low activity μW range sensor nodes.

ECG intervals such as QRS, QT and PR provide significant information and are widely used as clinical parameters for diagnosing cardiac diseases. This paper presents a novel QRS detection technique based on Curve Length Transform (CLT) and a refined delineation of P-wave and T-wave using Discrete Wavelet Transform (DWT). The proposed technique was verified using the PhysioNet database. The QRS detection achieved a sensitivity of 98.59% and a positive predictivity of 97.86%. The QRS duration, QT interval and PR interval had a mean error of -1.56± 28.8ms, -5.39± 42.4ms and 0.86± 40.3ms respectively. The proposed algorithm is computationally efficient and is simpler to implement in hardware, hence, will lead to a faster execution time, smaller design area and consequently low power consumption.

In this paper, we address the problem of MultiPoint Relay (MPR) node disconnection due to mobility in Vehicular ad-hoc networks (VANETs) using the cluster-based Quality of Service Optimized Link State Routing (QoS-OLSR) protocol. The protocol uses MPR nodes to establish communication among the clusters. MPR disconnection represents a major challenge in VANETs, due to the frequent change in the network topology. Consequently, the performance of the routing protocol will be weakened as it adversely affects the connectivity level of the network. Thus, our solution is a new cluster-based QoS-OLSR protocol based on intelligent water drop algorithm that is capable of (1) selecting the best set of MPR in terms of QoS (2) dealing with the MPR disconnection as it selects alternatives to assure a connected network (3) maintaining a reliable MPR failure management process. Simulation results demonstrate that the proposed model succeeds in improving the network connectivity and stability, reducing both the overhead and the path length, and increasing the packet delivery ratio compared to the original QoS-OLSR.

This paper introduces a dramatically novel traffic signs recognition (TSR) system that can perform traffic sign detection and tracking simultaneously. The proposed approach utilizes intensity images and the depth images, in parallel, to robustly detect and track traffic signs in real-time. Additionally, we suggest to supplement the ordinary traffic signs with the corresponding quick-response (QR) code plates that inherent the many advantages of the QR-codes, introducing the concept of QR-TSR systems.

The present paper is devoted to the evaluation of energy detection based spectrum sensing over different multipath fading and shadowing conditions. This is realized by means of a unified and versatile approach that is based on the particularly flexible mixture gamma distribution. To this end, novel analytic expressions are firstly derived for the probability of detection over MG fading channels for the conventional single-channel communication scenario. These expressions are subsequently employed in deriving closed-form expressions for the case of square-law combining and square-law selection diversity methods. The validity of the offered expressions is verified through comparisons with results from respective computer simulations. Furthermore, they are employed in analyzing the performance of energy detection over multipath fading, shadowing and composite fading conditions, which provides useful insighs on the performance and design of future cognitive radio based communication systems.

Abstract Automatic dependent surveillance‐broadcast is an emerging surveillance technology for the future “e‐enabled” aircrafts, which will make it possible for aircrafts to share their location data with neighboring aircrafts, ground controllers, and other interested parties. In order to provide the automatic dependent surveillance‐broadcast communications with a high level of accuracy and integrity, a reliable authentication mechanism is required. So far, however, very few cryptographic solutions have been offered to achieve this in the literature. Even existing solutions have faced the following challenges: (i) the authentication solutions based on regular digital signature require complex management of public‐key infrastructureell; and (ii) signing messages exchanged or broadcast frequently in aircraft‐to‐aircraft and aircraft‐to‐ground communication modes can cause a computational bottleneck easily. In order to address these challenges, we take a fresh approach to building up an authentication framework by introducing a new online/offline identity‐based signature scheme. Our scheme will resolve the public‐key infrastructure management issue by using the identities of aircrafts as public keys and will achieve a high efficiency through online/offline signature generation. Copyright © 2014 John Wiley & Sons, Ltd.

Cloud computing is an emerging paradigm that provides scalable computing and storage capabilities where resources are accessed on a pay-as-you-go basis. Software as a Service (SaaS) applications are hosted in the cloud and made available as services for tenants' organizations over a network. To achieve reusability in cloud computing, software and hardware resources are shared among multiple tenants. Conventional multitenant SaaS applications provide the same set of services for all tenants thus resulting in one-size-fits-all applications. However, as tenants may have different requirements, customizable SaaS solutions are needed. To accommodate evolving tenants' requirements, the SaaS instance should evolve systematically. In this paper, we present a multitenant single instance SaaS evolution platform based on Software Product Lines (SPLs). The platform specifies a set of evolution rules, based on feature modeling, that govern evolution decisions. We also present the early implementation phases of the proposed approach based on SPLs and Model Driven Architecture (MDA) concepts.

Recording the electrical activity of the heart over a period of time as detected using electrical sensors is referred to as Electrocardiography (ECG). ECG is recorded as a collection of signal waves that has repetitive patterns. These patterns are usually used in the complex diagnosis process through which ECG may indicate certain problems related to the heart or other parts of the body. Despite the extensive studies conducted on the analysis of ECG signals and their thorough analysis, there is a lack of a formal model that validate their specifications, which results in several inconsistencies and problems in their interpretations and usage. This, on the other hand, may lead to ambiguities and incompleteness in the methods that are developed utilizing ECG specifications and their features. Therefore, in this paper we propose a method to formalize and validate the specifications of ECG signals in Event-B. We formally define the waves of ECG and their relation, and then formalize and validate several properties about their behavior.

In recent years, network intrusion detection systems (NIDS) have faced a serious throughput challenge as a result of the rapid increase of network links to 1 and 10 Gbps rates. Consequently, this calls for NIDS to have wire-speed packet processing and real-time detection of malicious traffic. Snort is the most popular NIDS. Snort is an open source software-based NIDS and runs as a single threaded application. Snort processing and detection capabilities can be limited in networks with 1 and 10 Gbps network links. To overcome such a limitation, we present a design and implementation of two layer NIDS for accelerating Snort detection. The design combines hardware and software components whereby Snort operates as the second line of defense after hardware-assisted inspection of packet headers. In our design, Snort's frequently used rules are offloaded from Snort to a NetFPGA-based hardware layer. The NetFPGA implementation is based on Bloom filter to analyze and filter incoming packets with header fields matching those of frequently used rules. The second line of defense will dynamically offload the most frequently triggered rules to the NetFPGA and will only be executed if deep packet analysis is required for the incoming packet. The experimental results show a significant improvement in the CPU usage and an enormous reduction in packet loss when using Snort with NetFPGA filtering.

This paper presents a new fast locking phase lock loop architecture for frequency synchronization and tracking. The proposed Hyperbolic Σ-Δ No Delay Tanlock Loop (NDTL) has an extended lock-in range and an improved time jitter. The loop has an intentionally introduced hyperbolic nonlinearity, modified Σ-Δ blocks, and finite state machine (FSM), to adapt the loop filter, extending the locking range and improving the timing jitter. The proposed hyperbolic NDTL architecture performs well even in wireless communication systems with high Doppler shift (e.g. vehicular communications) that might cause the system to lose stability. The simulation results under various test scenarios demonstrate that the new architecture offers robust performance in terms of lock-in range, acquisition time, and timing jitter.

This paper discusses the design and implementation of a prototype system which integrates various existing technologies for home monitoring and control that fits with the future smart home concept. The system provides two way communications between home appliances /electronics devices, and a mobile phone. The home devices which are connected wirelessly using Bluetooth technology to a home server can be monitored and controlled via the mobile phone using a portable MIDlet application. The prototype system supports three main services: monitoring the status of devices; controlling their setting through configurations that are device dependent; and periodic notification of the status of all devices. The wireless technologies to realize the project are GSM and Bluetooth. J2ME for the mobile application, Java for the server application, and C for the microcontroller application are the programming languages used in the prototype system.

This paper presents a study that compares the architectures and study’s the performance of some of the major integer multiplication algorithms. This is achieved through a simulation environment that at this stage implements four major multipliers in C++ programming language and implements the same architectures in an FPGA prototype system. The environment is a flexible one and has a well-designed user interface that makes it suitable for educational use. It enables the user to emulate the multipliers for various data inputs and observe the type of operation being executed. Handle-C was used for synthesis and subsequently implementation of the multipliers in an FPGA. The multipliers involved in this study are Hennessy, carry save, ripple carry array and Wallace tree. The performance of each multiplier is assessed through a study of its area and real-time complexities.

This paper proposes an adaptive time delay digital tanlock loop architecture with enhanced performance. The new loop includes an error-sensing block that monitors the sample values in the delayed path and subsequently adjusts the digital filter gain before the system goes out of lock. Simulation and FPGA implementation show that the loop can efficiently handle large frequency disturbances that may otherwise result in out of lock conditions