Fence region constraints are essential in cell placement, as they can enhance design convergence speed and improve placement quality. This paper introduces a multilevel framework approach to tackle this challenge while maintaining placement quality and reducing complexity. First, the coarsening stage utilizes a fence region aware clustering to avoid inappropriate groupings. Next, recursive quadratic programming is employed to achieve a better initial cell distribution. Previous methods may result in longer wire-length because they typically assign fence objects to their placement regions before distributing cells over a placement region. To mitigate wirelength increases caused by overly restrictive constraints, our refinement stage uses a three-phase approach to gradually adjust the placement regions of fence objects. Additionally, cells are distributed across desired regions using an analytical placement formulation that includes a fence region aware penalty term. Experimental results demonstrate that our methodology achieves improved wirelength and routability while effectively managing fence region constraints.

Even though routability is of great concern to a recent global placement algorithm, there still exists a large room to improve it. To make legalization more easier and get a better placement, this article proposes an iterative approach to refine cell locations after global placement, where wirelength and routability are separately optimized in each iteration. It first moves cells to better locations to reduce wirelength. Unlike previous approaches, our approach guarantees that no wirelength will be increased so that the previous optimization result can be better maintained. Moreover, we propose a delicate procedure to move cells according to their gain values to reduce the largest wirelength. Next, the whitespace re-allocation approach is applied to redistribute whitespace over a chip to improve routability without changing relative locations of cells. To ensure that enough space will be allocated to the most routing congestion regions, we propose a sigmoid function to increase routing demands of regions according to their routing overflows and number of pins. The experimental results show that our methodology can obtain shorter wirelength and better routability in industrial designs when compared to other approach.

Cell placement remains a big challenge in the modern VLSI design especially in routability. Routing overflow may come from global and local routing congestion in a placement. To target on resolving these problems, this paper proposes two techniques in a global placement algorithm based on an analytical placement formulation and the multilevel framework. To remove global routing congestion, we consider each net as a movable soft module and propose a novel congestion-aware net penalty model so that a net will receive a larger penalty if it covers more routing congested regions. Therefore, our placement formulation can be more easier to move nets away from routing congested regions than other approaches and has less impact on wirelength. In addition, to relieve local congestion, we propose an inflation technique to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. The experimental results demonstrate that our approaches can get better routability and wirelength compared to other approaches such as NTUplace4h, NTUplace4dr, and RePlAce.

A novel asynchronous transfer mode (ATM) switching fabric using three-dimensional optical code division multiple access (CDMA) technology is presented. The proposed three-dimensional codes, temporal/spatial/wavelength (TSW) codes, have out-of-phase autocorrelation and cross-correlation equal to zero and one, respectively. Spectral slicing technology is utilized to achieve wavelength encoding and decoding. The results show that the switching fabric has no internal blocking and the number of input/output ports can reach up to 1369. The cell loss without considering the output blocking is smaller than 10/sup -8/. The total throughput can be as large as 1.1 Tbit/s.