This paper describes an architecture based on a serial iterative algorithm for Image Connected Component Labelling with a hardware complexity O(N) for an NxN image. The algorithm iteratively scans the input image, performing a recursive non-zero maximum neighbourhood operation. A complete forward pass is followed by an inverse pass in which the image is scanned in reverse order. The process is repeated until no change in the image occurs. The algorithm has been coded in Handel C language and targeted to a Celoxica RC1000-PP PCI board, which is based on a Virtex XCV2000E-6 FPGA. The whole design was fully implemented and tested on real hardware in less than 24 man-hours of work. The implementation speed (pixel throughput) is virtually independent of the image size and is equal to ~34MHz. For 1024x1024 input images, the whole circuit consumes 566 Slices and 5 BlockRAMs and can run at 34 MHz, leading to a 32 pass/sec performance.