International audience

International audience

This paper explores the application of reinforcement learning algorithms to the problem of calibrating and optimizing the performance of an integrated millimeter-wave (mmW) power amplifier (PA). The proposed calibration algorithm is aimed at compensating performance degradation while optimizing power efficiency, by finding the optimum values of a set of on-chip tuning knobs. The developed calibration solution is based on a multiagent deep reinforcement learning algorithm, in which a number of reinforcement learning agents learn to collaborate in order to optimize the complete set of specifications of the circuit under calibration. The proposed technique is validated based on post-layout simulation results of a tunable 60 GHz PA case study implemented in STMicroelectronics 55 nm CMOS technology.

Due to their continuous nature across all the inversion regions of MOS transistors, charge-based models are a promising analytical tool for preliminary design sizing that brings the advantages of simplicity and accuracy. These models allows for the efficient exploration of a design space while reducing the computational burden associated to complete compact models. In this paper, a method to analyze the dynamic and frequency performances of a single-ended inverter-based ring oscillators is presented. The proposed analysis is based on the time-domain evaluation of the loading currents, as well as of the input and output voltages of the ring oscillator’s constituent inverters, using the Euler method. The novelty of this approach is the use of a 5-parameter charge-based model that considers short-channel effects. The proposed analysis is tested on a practical implementation in 28nm FD-SOI CMOS technology and the results, including the maximum achievable frequency and dynamic efficiency are compared to those obtained using the UTSOI2 model.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the$7^{th}$local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the$3^{rd}$,$5^{th}$, and$7^{th}$LO harmonics, 13 dB gain, 13.3 dB NF, −3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of$0.62\times 0.22~mm^{2}$.

This article proposes a general approach to accurately model the N-path filters and mixers, with the double purpose of bringing a better insight in the frequency transposition phenomena and opening the door towards a more general discussion concerning NPF-NPM and their outstanding properties as passive circuits. Thanks to a Fourier transform analysis, some mathematical equations are rigorously derived for both filtering and mixing voltage gains. The analysis is compared with ideal simulations for various sets of parameters: source impedance$R_{a}$, load impedance$R_{L}$, switch resistance$R_{sw}$, capacitive path$C_{L}$. Some error curves are extracted validating the initial hypotheses for the model in a given range of capacitances values. As a proof of concept, it is shown that the model complies with the measurements results with very good accuracy. The error is less than 10.5% on the two first harmonics prediction.

This work presents a survey based on more than 200 published papers related to sub-6 GHz wideband LNAs [1]. It investigates the trends with respect to the technology node. Moreover, it proposes a comparison between the most used topologies regarding their main performance metrics such as the gain, bandwidth, noise figure, power consumption and linearity. Based on this study, analytical predictions can be verified and appropriate architectures targeting a given set of specifications can be easily selected. The analysis highlights also the performance improvements and design trade-offs of design enhanced solutions such as noise cancelling and gm-boosting architectures.

This paper presents a simple and efficient methodology for LNA design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple but accurate 7 parameter-based model valid in all regions of operation and allows an accurate preliminary sizing based on an analytical study. The proposed model describes the main short-channel effects in advanced technologies and allows an analytical evaluation of the LNA nonlinearity. A use case using a 28 nm FD-SOI technology is proposed to reflect that the methodology is well suited for designs at weak to moderate inversion level in an advanced technology for which simulation-based studies are often used for early sizing.

An on-chip high-frequency sinusoidal signal generator with a calibration circuit based on a coarse-fine delay cell is presented in this work. The proposed signal generator is based on harmonic cancellation by adding scaled and time-shifted versions of a periodic signal. However, as we increase the target frequency of the generated signal, harmonic cancellation can be severely degraded by timing issues, degrading in turn the spectral purity of the generated signal. This paper proposes an architecture of a harmonic cancellation-based sinusoidal signal generator including a calibration circuit. The calibration circuit is based on a coarse-fine delay cell that can correct timing inaccuracies. Postlayout simulations of the proposed generator in FD-SOI 28 nm technology show a THD better than −60 dB in the frequency range from 173 MHz to 2 GHz.

Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining time-shifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than -60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.

This paper describes an on-chip instrument for the estimation of absolute and period random jitter of clock signals in the GHz range with a sub-picosecond resolution. A self-referenced technique is used to remove the need of a very clean external reference clock. The instrument has been designed in STMicroelectronics 28 nm FDSOI technology. By exploiting the fine delay control which can be achieved with this technology, simulation results haven shown a resolution down to 100 fs for GHz clock signals with a simple calibration procedure. The instrument meets the requirement of a small footprint while using a standard digital test interface to transfer data. It can be configured in different ways to suit the resolution and frequency of operation requirements.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on high-speed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.

This Special Issue is a selection of the best articles presented at the 18th IEEE International NEWCAS Conference (NEWCAS) 2020 that was held in Montreal, Canada, on June 16–19, 2020. As an Interregional flagship conference of the IEEE Circuits and Systems Society (CASS), this conference covers a wide spectrum of topics, research, and practice in the fields of circuits and systems, and offers an international forum for exchanging ideas and results.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection.

This paper describes a BIST technique for the static linearity test of$V_{cm}$-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the$V_{cm}$-based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.

The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

This work presents the design, integration and experimental validation of an on-chip sinusoidal signal generator for analog and mixed signal Built-In Self-Test applications. The integrated generator is based on a calibrated harmonic cancellation strategy, previously presented by the authors, that consists in combining five digital square-waves with appropriate phase-shifts and scale weights. The generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are then scaled and combined using controlled current sources. The proof-of-concept prototype of the sinusoidal signal generator was integrated in STMicroelectronics 28 nm FDSOI technology and characterized in the laboratory to validate the feasibility of the proposal. Obtained results show a performance of 52 dB of SFDR for a generated sinusoidal signal at 166.67 MHz. The generator was tested in an operation frequency range from 1 MHz to 333 MHz.

Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.

The functional test of millimeter-wave (mm-wave) circuitry in the production line is a challenging task that requires costly dedicated test equipment and long test times. Machine learning indirect test offers an appealing alternative to standard mm-wave functional test by replacing the direct measurement of the circuit performances by a set of indirect measurements, usually called signatures. Machine learning regression algorithms are then used to map signatures and performances. In this work, we present a generic and automated methodology for finding an appropriate set of indirect measurements and assisting the designer with the necessary Design-for-Test circuit modifications. In order to avoid complex design modifications of mm-wave circuitry, the proposed strategy is targeted at generating a set of non-intrusive indirect measurements using process variation sensors not connected to the Device Under Test (DUT). The proposed methodology is demonstrated on a 60 GHz Power Amplifier designed in STMicroelectronics 55 nm BiCMOS technology.

This work presents a strategy for static linearity self-testing of successive-approximation analog to digital converters (SAR ADCs) with the goal of reducing test time. The proposed test technique takes advantage of the SAR ADC architecture to drastically reduce the number of necessary measurements for a complete static linearity characterization. Moreover, we show that static linearity measurements can be performed on-chip without the need of a test stimulus generator, by generating the major carrier transitions of the SAR ADC and acquiring them with a low resolution ADC. The proposed test circuitry is reduced to a simple incremental ΣΔ ADC. The technique is validated with behavioral simulations and the design trade-offs of the proposed test circuitry are explored.

Testing analog, mixed-signal and RF (AMS-RF) circuits represents a significant cost component for testing complex SoCs. Moreover, AMS-RF test generation and validation are still largely handcrafted tasks that rely on expert design knowledge for each particular Device Under Test (DUT). Mixed-signal test automation has been sought by the test community for the last decades, trying to mimic the success of digital test approaches. Indeed, in the digital domain, test is vastly automated and standard techniques are already available (ATPGs, BIST, scan registers, etc.). In the last decade, a methodology based on leveraging the power of machine learning algorithms has been proposed for AMS-RF circuits that opens the door to a higher level of automation. In this paper we review recent results in this line and try to put together what could be such a complete methodology and what remains to be done.

Beam-forming techniques using phased arrays are one of the most promising solutions for the practical implementation of future high-data-rate point-to-point communication protocols. The functionality of phased arrays is based on the use of phase shifters that should provide an accurate and controllable phase difference between the different paths of the array. However, the integration of phase shifters in current nanometric technologies is prone to imperfections that may affect the intended phase shift and degrade the performance of the antenna array. This requires extensive testing and calibration and represents a bottleneck in the production line of these system. In this work, we propose a simple Oscillation-Based Test technique that may be suitable for Built-In Self-Test applications of phase shifters. The technique is demonstrated on a Reflection-Type Phase Shifter implemented in a 55 nm BiCMOS technology. Electromagnetic and electrical simulation results show the feasibility of the proposed technique.

Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system - i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

This work presents the design of a high-frequency on-chip sinusoidal signal generator based on a calibrated harmonic cancellation strategy. The proposed generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using a harmonic cancellation strategy in a simplified current-steering DAC with only five branches. The proposed architecture allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28 nm FDSOI design are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 70 dB of SFDR for a generated sinusoidal signal at 166 MHz.

Current mixed-signal BIST approaches are aimed to move test instrumentation on-chip to reduce the cost of test. However, this can result in a high overhead even for non-time critical DSP tasks that could be executed remotely if a suitable access was available. The new IEEE 1687-2014 standard provides such a portable and efficient infrastructure and can allow decoupling of digital and analog development extremely early in the design flow. In this paper, we demonstrate the approach by applying it to a ΣΔ modulator BIST. In this case study, we exploit 1687 to offload the computationally-heavy spectral analysis that may be responsible of nearly 80% of the total BIST overhead.

This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip implementation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

Machine learning indirect test - also known as Alternate Test- has shown its potential to reduce test cost while maintaining an interpretation of the results compatible with the standard specification-based test. Since its introduction, many papers have been proposed to refine the idea and address its shortcomings. In particular, the issue of early validation of the test at the design stage has been considered and some methodologies have been proposed to assess test quality. These methodologies rely essentially on Monte Carlo simulations. In this paper, we propose a set of thought experiments to show that small inaccuracies and variations in the Monte Carlo models included in current technology process design kits may have a significant impact in the validation of machine learning indirect test, in particular in the estimation of test quality metrics. Despite of this, machine learning indirect test has actually succeeded in actual industrial cases. Some hints are thus given to the conditions that the test has to fulfill to guarantee good results.

The high cost of mixed-signal circuit testing has sparked a lot of interest for developing alternative low-cost techniques. Although it is rather straightforward to evaluate an alternative test technique in terms of test cost reduction, proving the equivalence between an alternative and the standard test technique in terms of test metrics, before actually deploying the alternative test technique in production, is very challenging. The underlying reason is the prohibitive simulation effort that is required. Existing test metrics evaluation methodologies are efficient only for circuits that can be simulated fast at transistor-level. In this paper, we propose a test metrics evaluation methodology for circuits with long simulation times that is based on a combination of behavioral modeling and statistical blockade. The methodology is demonstrated on a built-in self-test strategy for ΣΔ analog-to-digital converters.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Linearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators.

Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of ΣΔ ADCs based on a digital ternary stimulus together with an advanced simulation framework for its validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioural simulations, and statistical tools. To show the feasibility of our approach, we use the proposed validation framework to compare the ternary stimulus with a digital bitstream stimulus, as well as with a standard high-resolution analog sine-wave stimulus.

This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.

This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal.

This work demonstrates that multi-VDDconditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90 nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude between 0°C and 100°C with negligible impact on the phase noise. Worst case estimations of the VCO phase noise after layout parasitic extraction are -110.1dBc/Hz and -126.6dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. Its nominal current consumption is 198μA (plus 22.5μA for biasing) and it occupies 370×530μm2.

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

This paper presents a practical implementation of a network analyzer for analog BIST applications. The network analyzer consists of a sinewave generator and a sinewave evaluator based on switch-capacitor techniques. Both the generator and the evaluator have been integrated in a 0.35 mum CMOS technology. The functionality of the system has been proved in the lab. For this purpose, a demonstrator board has been developed including the proposed network analyzer and a filter as DUT Measurements in the lab demonstrate a dynamic range of 70dB in the frequency range up to 20 kHz.