Modern digital circuits are, with each technological evolution, increasingly affected by Single Event Upsets (SEUs). In this paper we propose a static analysis approach for the estimation of the SEU sensitivity of the system under design by identifying untestable faults. The approach relies on a formal specification language to model circuits at the gate-level and on the Linear Temporal Logic (LTL) to express untestability properties that are then evaluated using a model-checking tool. The proposed approach can be applied early during the design process, since it can be individually applied to sub-systems as soon as they are designed, before the whole system is implemented and since it does not require a specific workload to be defined. The approach has been implemented and applied to a set of circuits from the ITC99 benchmark and has been validated against fault injection experiments.

In this paper, a comparison between two HDL-based fault-injection methods, FT-UNSHADES and NETFI, is presented. Fault-injection campaigns were performed on a third party example, named KECCAK sponge function family circuit dedicated for cryptography which is available as an open core. The comparison of both methodologies shows a similarity in the results and enlightens a problem that affects fault-injection systems related to how the synthesis and the simulation is made.

Real-time traffic sign recognition has been object of in-depth studies in the last years, and it has become one of the main pillars of Driver Support Systems (DSS). The purpose of this paper is to show a complete implementation of a real-time traffic sign recognition working on reconfigurable logic. The system has been proved to work at 60 frames per second with a video resolution of 1280×720 pixels, and is able to handle simultaneously up to 8 road signs in the same frame.

Nowadays, integrated circuit technologies are increasingly being more susceptible to ionizing radiation effects. In order to assess the reliability of a digital system performing a specific application and to identify the most critical failure effects, radiation experiments and fault injection campaigns are usually performed, which may be costly and time-expensive. This paper proposes a fully automated, practical methodology for accelerating Single-Event-Upset (SEU) fault injection campaigns in digital circuits. The main underlying principle is based on the correlation between the effects of the SEU fault model with the Stuck-At (SA) one. Circuital and functional analysis and experimental case studies confirm the effectiveness of the proposed solutions.

The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. The methodology is supported by an infrastructure that permits to easily combine hardware/software soft errors mitigation techniques in order to best satisfy both usual design constraints and dependability requirements. It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic generation of protected source code (hardened code). Two case studies are presented. In the first one, several software-based mitigation techniques are implemented and evaluated showing the flexibility of the infrastructure. In the second one, a customized fault tolerant embedded system is designed by combining selective protection on both hardware and software. Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. Among the developed software-based mitigation techniques, a novel selective version of the well known SWIFT-R is presented.

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the co-design of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.

The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolated-from-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.

Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular Redundancy need to be adopted in order to guarantee the desired fault tolerance degree. While effectively increasing the fault tolerance capability, these techniques introduce an important performance degradation and a dramatic area overhead, that results in higher design costs. In this paper, we propose an innovative design flow that allow the implementation of fault tolerance circuits in SRAM-based FPGA devices with different fault tolerance capability degrees. We introduce a new metric that allows a designer to precisely estimate and set the desired fault tolerance capabilities. Experimental analysis performed on a realistic industrial-type case study demonstrates the efficiency of our methodology.