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Mihai Burcea

dblp:83/3899 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 2017
0009-0001-9891-4622ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Theory of computation · 2 · 1 first-authorArtificial intelligence and machine learning · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Parallel and multicore computing · 100%
Software engineering, system software, and programming languages
2 papers
Concurrent programming · 100%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
transactional memory
0.422017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017
Transactional memory support for scalable and transparent parallelization of multiplayer games · EuroSys 2010
Parallel and multicore computing › transactional memory
hardware transactional memory
0.312017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017
Parallel and multicore computing › transactional memory
hybrid transactional memory
0.312017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017
Concurrent programming › transactional memory
software transactional memory
0.112010
Towards scalable and transparent parallelization of multiplayer games using transactional memory support · PPoPP 2010
Concurrent programming
transactional memory
0.112010
Towards scalable and transparent parallelization of multiplayer games using transactional memory support · PPoPP 2010
Parallel and multicore computing
parallel programming models
0.112010
Transactional memory support for scalable and transparent parallelization of multiplayer games · EuroSys 2010
Parallel and multicore computing › transactional memory
software transactional memory
0.112010
Transactional memory support for scalable and transparent parallelization of multiplayer games · EuroSys 2010
Concurrent programming › synchronization
locking
0.012010
Towards scalable and transparent parallelization of multiplayer games using transactional memory support · PPoPP 2010
Concurrent programming
synchronization
0.012010
Transactional memory support for scalable and transparent parallelization of multiplayer games · EuroSys 2010

Methods — techniques the papers use, named apart from their topics

software transactional memory · 0.4software fall-back path · 0.3
YearPublicationVenuePosition
2017 POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support
abstract
In this work, we introduce and experimentally evaluate a new hybrid software-hardware Transactional Memory prototype based on Intel's Haswell TSX architecture. Our prototype extends the applicability of the existing hardware support for TM by interposing a hybrid fall-back layer before the sequential, big-lock fall-back path, used by standard TSX-supported solutions in order to guarantee progress. In our experimental evaluation we use SynQuake, a realistic game benchmark modeled after Quake. Our results show that our hybrid transactional system,which we call HythTM, is able to reduce the number of transactions that go to the sequential software layer, hence avoiding hardware transaction aborts and loss of parallelism. HythTM optimizes application throughput and scalability up to 5.05x, when compared to the hardware TM with sequential fall-back path.
Arnamoy Bhattacharyya, Mike Dai Wang, Mihai Burcea, Allen Deng, Sai Varikooty, Shafaaf Hossain, Cristiana Amza
PPoPP3
2013 Online Multi-dimensional Dynamic Bin Packing of Unit-Fraction Items
Mihai Burcea, Prudence W. H. Wong, Fencol C. C. Yung
CIAC1
2013 Scheduling for Electricity Cost in Smart Grid
Mihai Burcea, Wing-Kai Hon, Hsiang-Hsuan Liu 0001, Prudence W. H. Wong, David K. Y. Yau
COCOA1
2012 An 8/3 Lower Bound for Online Dynamic Bin Packing
Prudence W. H. Wong, Fencol C. C. Yung, Mihai Burcea
ISAAC3
2010 Transactional memory support for scalable and transparent parallelization of multiplayer games
abstract
In this paper, we study parallelization of multiplayer games using software Transactional Memory (STM) support. We show that the STM provides not only ease of programming, but also better performance than that achievable with state-of-the-art lock-based programming, for this realistic high impact application.
Daniel Lupei, Bogdan Simion, Don Pinto, Matthew Misler, Mihai Burcea, William Krick, Cristiana Amza
EuroSys5
2010 Towards scalable and transparent parallelization of multiplayer games using transactional memory support
abstract
This work addresses the problem of parallelizing multiplayer games using software Transactional Memory (STM) support. Using a realistic high impact application, we show that STM provides not only ease of programming, but also better performance than that achievable with state-of-the-art lock-based programming.
Daniel Lupei, Bogdan Simion, Don Pinto, Matthew Misler, Mihai Burcea, William Krick, Cristiana Amza
PPoPP5