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Andreas Farid Pour

dblp:83/39 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 70% Hardware reliability and fault tolerance · 30%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.011993
Performance Implications of Tolerating Cache Faults · IEEE Trans. Computers 1993
Memory systems › cache › cache technology
fault-tolerant cache
0.011993
Performance Implications of Tolerating Cache Faults · IEEE Trans. Computers 1993
Memory systems › cache
cache performance
0.011993
Performance Implications of Tolerating Cache Faults · IEEE Trans. Computers 1993

Methods — techniques the papers use, named apart from their topics

trace-driven simulation · 0.0
YearPublicationVenuePosition
1993 Performance Implications of Tolerating Cache Faults
abstract
The authors investigate how much cache miss ratios increase when blocks are disabled. It is shown how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, an efficient approach is developed for calculating the exact distribution of miss ratio increases from all fault patterns, and this approach is applied to the ATUM traces (see A. Agarwal et al., 1986). Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size and is negligible (>
Andreas Farid Pour, Mark D. Hill
IEEE Trans. Computers1