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Abhijeet Dugar

dblp:83/4829 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 30% Distributed systems · 30% Processor architecture and microarchitecture · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
fault tolerance		 0.011989
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive · IEEE Trans. Computers 1989
Processor architecture and microarchitecture › atomic operations
fetch-and-add synchronization		 0.011989
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive · IEEE Trans. Computers 1989
Interconnection networks and networks-on-chip › switching network
multistage interconnection network		 0.011989
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive · IEEE Trans. Computers 1989
Performance modeling and evaluation › performance evaluation methodology
simulation and analytical modeling		 0.011989
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive · IEEE Trans. Computers 1989
YearPublicationVenuePosition
1989 The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive
abstract
The combining multistage interconnection network uses 4*4 switches as switching elements and introduces an extra stage of such switches and links to create four independent paths between any source-destination pair. Four copies of every message are sent through the network simultaneously. The scheduling discipline, the design of the switching elements to support the discipline, and the theoretical proof of correctness of the design constitute the key contributions of this study. Estimates are provided of various network parameters as a function of the workload, using analytical models and detailed network simulations. It is shown that the proposed design for fault tolerance is more cost-effective than the brute-force technique of having multiple copies of the network.>
Prithviraj Banerjee, Abhijeet Dugar
 IEEE Trans. Computers2
1986 A Fault-Tolerant Interconnection Network Supporting the Fetch-And-Add Primitive
Prithviraj Banerjee, Abhijeet Dugar
 ICPP2