Automatic test equipment (ATE) for highperformance memory devices needs to transmit and receive ultra-high-speed data/clock waveforms with high fidelity. So far, this has been achieved by applying intricate calibrations with external equipment, which requires significant time, cost, and effort. This paper proposes a method for estimating S-parameters of signal paths to DUT using time-domain reflectometry (TDR), which enables automated calibration for a large number of ATE pins by utilizing built-in drivers and comparators. The proposed method compensates for the effects of reflections from the signal path and the characteristics of the comparator circuit, which affect the TDR measurement results, and enables the accurate prediction of the waveform at the calibration point. Furthermore, without the necessity for external equipment, the proposed method realizes the calibration of a massive number of pins in a short time at a low cost.

This paper presents a 10ps-order flexible resolution time-to-digital converter (TDC) consisting of only Lookup Tables and Flip-Flops that can be applied to legacy FPGAs, which is industry friendly. The proposed TDC is a Vernier delay-line based TDC. By using MUX chains as the delay adjustable buffers, it realizes flexible and high resolution 10ps-order TDC. By controlling the control values of each MUX chain independently, the nonlinearity of TDC is compensated. In the evaluation using the AMD Artix-7 FPGA, the DNL and INL were [−0.26 LSB, 0.91 LSB] and [−0.84 LSB, 2.27 LSB], respectively, at a resolution of 8.92 ps.

This paper introduces a highly reliable delay-based weak FPGA Physically Unclonable Function (PUF), leveraging stochastic delay measurement with PLLs. The delay of delay-lines is precisely measured using the proposed fully synchronous stochastic delay measurement method. Thus, the reliability surpasses that of conventional PUFs that depend on asynchronous circuits or measurement. In the evaluation, the inter-chip HD of the proposed PUF without Spread Spectrum Clock Generator (SSCG) is 47.79%, and the intra-chip HD is 0.0052%, which is about 1/100 of the conventional PUFs. With SSCG, the inter-chip HD of the proposed PUF is 47.98%, and the intra-chip HD is 0.00092%, which is about 1/5 of the value in the absence of SSCG.

This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in offset pulse and an offset pulsewidth detection schemes. With several techniques, including a built-in coarse gain calibration mechanism, the proposed TS architecture overcomes a nonlinearity due to the signal propagation and gain mismatch between coarse and fine stages. The simulation results of the TDC implemented in a 0.18-μm standard CMOS technology demonstrate 2.0-ps resolution and 16-bit range that corresponds to ~130-ns input time interval with 0.08-mm2area. It operates at 3.3 MS/s with 18.0 mW from 1.8-V supply and achieves 1.44-ps single-shot precision.

This paper proposes a synthesizable digital LDO that is implemented with standard-cell-based digital design flow. With inverter chains as voltage-controlled delay lines, the difference between output and reference voltages is converted into delay difference, then compared in time-domain. Since the time-domain difference is straightforwardly captured by a phase detector that consists of a D-FF, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. The prototype of the proposed LDO is fabricated in 65 nm standard CMOS technology with 0.015 mm2area occupation. The measurement results show that with 10.4 MHz internal clock the tracking response to 200 mV switching of the reference voltage is ~4.5 μs and the transient response to 5 mA change of the load current is ~6.6 μs. The quiescent current consumed by the LDO core is as low as 35.2 μA at 10 mA load current, which leads to 99.6 % current efficiency.

A pulse generator (PG) for low power and low duty cycle applications is presented. The PG employs a CMOS switch and a quarter-wavelength transmission line resonator. Since the architecture does not involve feedback gain, the PG is theoretically capable to generate a pulse efficiently at high oscillation frequency (fosc), at which a transistor gain is limited. The PG also features a quick starting time and zero stand-by power. The PG is designed on a 0.18 μm CMOS flipped over a transmission line resonator, implemented by aluminum on a quartz substrate. The prototype consumes 5.4 pJ/pulse, with energy conversion efficiency (ECE) of 2.37% at foscof 11.5 GHz.

This paper proposes a breakdown-pixel-extraction architecture for SPAD sensor. The proposed readout circuit detects the breakdown pixels and their addresses are readout. Therefore, under the faint light environment, this SPAD sensor significantly improves the data readout efficiency. A 15 × 15 SPAD sensor was fabricated in a 0.18 um CMOS process, and a high speed readout is verified by measurement.

Mismatch of power supply integrity between an ATE and a customer board in semiconductor test can lead to test failures such as overkills and underkills. A technique is required to control the power supply impedance of an ATE by feedback control using compensation current injection so that it emulates the impedance of a customer board, eliminating test failures coming from the impedance difference between the two environment. This paper discusses an extension theorem for a multiple power domain with mutual interference, such as a SIMO. Simulation results showed very good agreement between our emulated ATE and the customer board power supply noise waveforms.

This paper proposes a new type of power supply circuit for automatic test equipment (ATE) that has ability to emulate arbitrary power supply impedance. It can emulate power supply impedance of customer environment so as to match the power supply voltage fluctuation waveforms of the ATE and of the customer environment, in order to eliminate overkills/underkills coming from the voltage fluctuation difference caused by the impedance difference between the ATE and a practical operating environment. Our technique adjusts the equivalent impedance by injecting compensation current by a current source attached in parallel with the power supply source. The compensation current is calculated and injected in realtime with a feedback manner based on the power supply voltage measurement with the impedance characteristics of ATE's original power delivery network (PDN) and the customer PDN. Experimental results of prototype circuits are demonstrated to show that the compensation current emulates the impedance, and the both power supply voltage fluctuation waveforms agree well. Limitations and applications of our method are also discussed.

This paper proposes a method for analyzing the power supply impedance at an on-chip power supply node in the device under test. The proposed method is based on an on-chip power measurement of a power supply voltage fluctuation with sweeping the frequency of the on-chip current load which sinks a square wave current, not sinusoidal. The method can extract the frequency characteristics of not only the magnitude but also the phase characteristic of the power supply impedance. Experimental results based on SPICE simulations proved that the proposed method can accurately measure the frequency characteristic of the power supply impedance. It is also confirmed that the extracted power supply impedance characteristics gives quite similar transient voltage waveforms to the target waveforms.

An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. Thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 1P5M 0.18 μm CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 22 ns. Such a speed is very important for SPAD-based sensors that need fast summation operations.

A Transmission-line-based Burst-pulse Generator (TPG) is proposed in this paper. The proposed architecture does not consume power in standby stage, so it is more suitable in a pulse system than a continuous wave generator. Also, the center frequency of the pulse can be higher than the Fmaxof a CMOS process, since the pulse oscillation need not be sustained. The architecture is modeled and simulated in a 0.18-µm CMOS process, then the performance is compared with a push-push oscillator, which is a conventional method to generate frequency higher than process's Fmax. It is shown that our TPG has better energy conversion efficiency up to a pulse duty cycle of 10%, and the oscillation frequency above 2Fmaxof the process is achieved.

It is believed that the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of an analog signal in advanced CMOS processes[1], [2]. The reasoning behind this is that operating voltage has been reducing, making the signal more vulnerable to noise power due to scaling. On the other hand, in time domain, scaling has resulted to increase in frequency and therefore design of faster circuits, while also contributing to reduction of jitter. However, this is a concept that has not yet been quantitatively examined. This paper aims at verifying the effectiveness of the time-domain circuits over voltage-domain circuits in terms of their dynamic range performances by simulations as well as by theoretical analysis, especially in the scaled nano-meter processes. It has been shown that for a given technology the time domain dynamic range is superior to the voltage domain dynamic range by a factor of (ωT/B)2where ωTis the unity gain frequency and B is the bandwidth.

This paper demonstrates our dynamic power integrity control for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the device under test (DUT). It injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. Experimental results of delay fault testing with 105 real silicon chips show that 48% of overkills/underkills due to the different power supply characteristics can be eliminated by our dynamic power integrity control. Furthermore, it was found that adjusting the magnitude of the power integrity control based on the chip-to-chip active power variation improves the correlation of the test results between the ATE and the customer environment, resulting in 95% of the overkills/underkills can be eliminated.

This paper, as a case study and tutorial, discusses testing methods for general PLL features and their operating margin. These methods can be applied all for analog-, digital- and PW-PLLs. There are various kinds of on-chip measurement macros which can be applied for the PLL testing, and for the direction toward digitally assisted analog circuit testing, it is shown that a digitally controlled variable delay and a time to digital converter have a big possibility for PLL testing using only digital signals.

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT). The proposed method controls the power supply voltage on an automatic test equipment (ATE) system in a feed-forward manner by supplying a compensation current into the power supply line based on the power supply voltage waveform difference between the ATE and the customer operational environment of the DUT. A method is described for calculating the compensation current from an impulse response of the device power supply (DPS) network in the ATE and a target power supply voltage waveform. Experimental results with a prototype circuit are demonstrated to confirm the proposed concept. The proposed method can emulate the power supply voltage waveform under a customer's operating condition that has never been tested before. Furthermore, this method can stabilize the power supply voltage of the DUT and realize an arbitrary power supply noise waveform profile. Limitations and applications of the proposed method are also discussed.

This paper presents an all-digital PMOS and NMOS process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit.

This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18 μm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18¿m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ±250ps input range.

In this paper, we propose an all-digital process variability and aging monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the infield monitoring of aging effects such as negative bias instability (NBTI) and channel hot carrier (CHC).

We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18mum CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.

In this paper, an all digital baseband data recovery algorithm using oversampling technique is presented. Our algorithm uses 5× clock to sample incoming data once around the middle. Sampling occurs exactly on the third clock after a data edge. If no data edge sensed, sampling occurs after five clocks from the previous sample. The system is designed to receive 50 Mbps data bit rate and uses a 250 MHz local clock to do the oversampling process. After injecting the clock with jitter at various magnitudes and frequencies, the design showed around 0.9 data Unit Interval (UIdata) jitter tolerance at frequencies higher than 25 MHz, in addition to a low Bit Error Rate (BER ≪ 10−11). The setup is implemented on an Altera Stratix II GX Field Programmable Gate Array (FPGA) while Agilent 81250 parallel Bit Error Ratio Tester (parBERT) is used to measure BER using Pseudo Random Bit Sequences (PRBS). Using 0.18 µm CMOS process, the design consumes as low power as 5 µW, which makes it effective for low power applications such as wireless image sensor nodes.

We have introduced the concept of the Moebius strip into LSI circuit design, realizing 8.4 FO4-Inverter throughput for any kind of digital logic circuit. The Moebius circuit operates in a logic gate level pipeline, and has error detection and error gate search features, using a self-timed architecture.

As the growing demand of mixed-signal designs as A/D, D/A and PLL integrated with large scale digital circuits, substrate noise becomes serious concern. On the other hand, the remedies using guard ring and decoupling capacitor do not have enough efficiency against high frequency noise due to their parasitic component. To suppress the impact of substrate noise, on-chip active noise cancelling technique using di/dt detector has been proposed (Nakura et al., 2004) and (Nakura et al., 2006). This paper introduces an exapmle design of feedforward active substrate noise canceling technique using multiple power supply di/dt detector and demonstrates the noise cancelling results by the measurement of 0.35 mum CMOS test chip.