A high-frequency electromagnetic-wave logging (HFEL) tool has been developed to detect the dielectric constant and resistivity of the sedimentary formation by measuring the phase difference and amplitude ratio synchronously. The single-parameter deconvolution method is a convenient tool for enhancing the vertical resolution of the curves and reshaping the curves themselves. This paper attempts to resolve the two parameters, the dielectric constant and the resistivity, which are employed in the deconvolution method from two responses: the phase difference and amplitude ratio. First, an adaptive dual-parameter deconvolution method for the HFEL dielectric constant and resistivity measurements is devised to enhance the vertical resolution of the tool and to more accurately extract the formation parameters, namely, the dielectric constant and resistivity. The advantages of this method are revealed in the numerical experiments on the synthetic and actual logging data. The adaptive dual-parameter deconvolution can be informative in the application of the deconvolution.

The electromagnetic propagation resistivity logging (EPRL) tool comprises one transmitter and a pair of receivers and measures the phase difference and the amplitude ratio (sometimes referred to as attenuation) across two receivers. Generally, the spatial response characteristics of the phase difference and the amplitude ratio can be summarized as follows: the amplitude ratio has large sensing volume and very low resolution than the phase difference. In this letter, a combined measurement method of the phase difference and the amplitude ratio (CPA) for EPRL is put forward by defining a new mathematical expression about the amplitude ratio. In this new mathematical expression, a so-called measure angle is introduced. By changing the measure angle, the CPA can provide a good tradeoff between the sensing volume and the resolution in the spatial response characteristics. Furthermore, the change of CPA curves that vary with the measure angle can be used to provide an alternative measurement which appears to be more applicable than the amplitude ratio.

This paper presents an efficient hardware architecture for scheduling connections on a fat-tree interconnection network for parallel computing systems. Our technique utilizes global routing information to select upward routing paths so that most conflicts can be resolved. Thus, more connections can be successfully scheduled compared with a local scheduler. As a result of applying our technique to two-level, three-level and four-level fat-tree interconnection networks of various sizes in the range of 64 to 4096 nodes, we observe that the improvement of schedulability ratio averages 30% compared with greedy or random local scheduling. Our technique is also scalable and shows increased benefits for large system sizes.

The maximum matching algorithm for bipartite graphs can be used to provide optimal scheduling for crossbar based interconnection networks. Unfortunately, maximum matching requires O(N3) time for an N x N communication system, which has limited its application to real-time network scheduling. In this paper, we show how maximum matching can be reformulated in terms of Boolean operations rather than the more traditional formulations. By taking advantage of the inherent parallelism available in custom hardware design, we introduce three Maximum Matching implementations in hardware and show how we can trade design complexity for performance. Specifically, we examine a Pure Logic Scheduler with three dimensions of parallelism, a Matrix Scheduler with two dimensions of parallelism and a Vector Scheduler with one dimension of parallelism. These designs reduce the algorithmic time complexity down to O(1), O(K), and O(KN), respectively, where K is the number of optimization steps. While an optimal scheduling algorithm requires K = 2N -- 1 steps, our simulation results show that the scheduler can achieve 99% of the optimal schedule when K = 9. We examine hardware and time complexity of these architectures for crossbar sizes of up to N = 1024. Using FPGA synthesis results, we show that a greedy schedule for various sized crossbars, ranging from 8 x 8 to 256 x 256, can be optimized in less than 20 ns per optimization step. For crossbars reaching 1024 x 1024 the scheduling can be completed in approximately 10 μs with current technology and could reach under 90 ns with future technologies.