Demo Data from EDBT 2026 / reviewers in the wild / expert
C.-S. Yeh
dblp:83/5629
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1984
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 79% Hardware accelerators and domain-specific architectures · 17% Parallel and multicore computing · 4% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1984 | Systolic Multipliers for Finite Fields GF(2m) · IEEE Trans. Computers 1984 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1984 | Systolic Multipliers for Finite Fields GF(2m) · IEEE Trans. Computers 1984 |
Integrated circuit design › finite field arithmetic
finite field multiplier |
0.0 | 1 | 1984 | Systolic Multipliers for Finite Fields GF(2m) · IEEE Trans. Computers 1984 |
Hardware accelerators and domain-specific architectures
systolic array |
0.0 | 1 | 1984 | Systolic Multipliers for Finite Fields GF(2m) · IEEE Trans. Computers 1984 |
Integrated circuit design › digital signal processing circuits
digital filter |
0.0 | 1 | 1983 | A Parallel Architecture for Digital Filtering Using Fermat Number Transforms · IEEE Trans. Computers 1983 |
Integrated circuit design
digital signal processing circuits |
0.0 | 1 | 1983 | A Parallel Architecture for Digital Filtering Using Fermat Number Transforms · IEEE Trans. Computers 1983 |
Parallel and multicore computing
parallel architecture |
0.0 | 1 | 1983 | A Parallel Architecture for Digital Filtering Using Fermat Number Transforms · IEEE Trans. Computers 1983 |
Methods — techniques the papers use, named apart from their topics
pipeline structure · 0.0fermat number transform · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1984 | Systolic Multipliers for Finite Fields GF(2m)abstractTwo systolic architectures are developed for performing the product–sum computation AB + C in the finite field GF(2m) of 2melements, where A, B, and C are arbitrary elements of GF(2m). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The first multiplier requires a smaller number of basic cells than the second multiplier. The second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively. To perform single computations both multipliers require the same computational time. In both cases the architectures are simple and regular and possess the properties of concurrency and modularity. As a consequence they are well suited for use in VLSI systems. C.-S. Yeh, Irving S. Reed, Trieu-Kien Truong |
IEEE Trans. Computers | 1 |
| 1983 | A VLSI architecture for digital filters using complex number-theoretic transformsabstractIn this paper a parallel architecture is developed to realize a digital filter. First a systolic array is used to compute a 248-point complex number-theoretic transform (CNT). Next an algorithm is developed to realize a digital filter that uses 248-point CNT's and a generalization of the overlap-save method. This algorithm solves the conflict between long transform lengths and a wide dynamic range associated with the number-theoretic transform. Finally this algorithm is mapped to a parallel architecture. This architecture is simple, regular and expandable, and, hence, is suitable for VLSI implementation. Irving S. Reed, C.-S. Yeh, Trieu-Kien Truong |
ICASSP | 2 |
| 1983 | A Parallel Architecture for Digital Filtering Using Fermat Number TransformsabstractIn this correspondence, a parallel architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT). In particular, a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao |
IEEE Trans. Computers | 3 |