Ising machines model nature dynamics to solve nondeterministic polynomial time (NP) hard combinatorial optimization problems (COPs). Because physical systems can naturally minimize their energy, these Ising machines have higher efficiency as compared to von Neumann architectures. This makes Ising machines attractive for tackling complex optimization problems mapped to the Ising Hamiltonian. In this paper, a highly scalable CMOS-compatible Ising machine design is proposed that leverages ring oscillator coupling under second-order sub-harmonic injection locking (SHIL). The proposed design is smaller and faster as compared to the state-of-the-art based on initial findings. Unlike traditional designs that use external injection locking signals or bulky LC oscillators, the proposed approach integrates both spin representation and SHIL signal generation directly on-chip using lightweight ring oscillators. The phase readout process is simplified by utilizing XOR gates for efficient spin readout. The initial results, obtained through SPICE simulations on 28nm FDSOI technology, confirm the feasibility of the proposed design. This approach presents a compact high-speed Ising machine with potential applications in solving a wide range of NP-hard problems.

Pseudo-random number generators (PRNGs) are essential in a wide range of applications, from cryptography to statistical simulations and optimization algorithms. While uniform randomness is crucial for security-critical areas like cryptography, many domains, such as simulated annealing and CMOS-based Ising Machines, benefit from controlled or nonuniform randomness to enhance solution exploration and optimize performance. This paper presents a hardware PRNG that can simultaneously generate multiple uncorrelated sequences with programmable statistics tailored to specific application needs. Designed in 65nm process, the PRNG occupies an area of approximately 0.0013mm2and has an energy consumption of 0.57pJ/bit. Simulations confirm the PRNG's effectiveness in modulating the statistical distribution while demonstrating high-quality randomness properties.

Nature-inspired computation is receiving increasing attention. Various Ising machine (IM) implementations have recently been proven to be effective in solving numerous combinatorial optimization problems including maximum cut, low density parity check (LDPC) decoding, and Boolean satisfiability (SAT) problems. In this paper, a novel method is presented to solve SAT or MAX-SAT problems with a CMOS circuit implementation. The technique solves a SAT problem by mapping the SAT variables onto quantized capacitor voltages generated by an array of nodes that interact through a network of coupling units. The nodal interaction is achieved through coupling currents produced by the coupling units, which charge or discharge capacitor voltages, implementing a gradient descent along the SAT problem’s cost function to minimize the number of unsatisfied clauses. The system also incorporates a unique low-complexity perturbation scheme to avoid settling in local minima, greatly enhancing the performance of the system. The simulation results demonstrate that the proposed SKI-SAT is a high-performance and low-energy alternative that surpasses existing software-based SAT solvers by significant margins, achieving more than 10 times faster solution and over 300 times less power.

Ising machines have shown great promise in solving combinatorial optimization problems (COPs) using nature-inspired computation with higher speed and efficiency over traditional von Neumann computing systems. CMOS-based implementations combine the maturity and scaling ability of CMOS with the efficacy of Ising machines. In this paper, a low-density parity-check (LDPC) decoding solution is implemented with a CMOS-based resistively-coupled Ising machine known as (QuBRIM), using multi-body interactions among CMOS-based Ising machine nodes for the first time. State-of-the-art CMOS-based Ising implementations currently utilize order reduction to solve problems with higher-than-quadratic terms. In this paper, a new mechanism is proposed to implement higher-than-quadratic terms on Ising machines without the need for order reduction. The proposed methodology is implemented and verified with CMOS technology using 45 nm Generic PDK (GPDK). High accuracy rates are reported for the LDPC decoder based on the proposed methodology, comparable to Normalized Min-Sum, Offset Min-Sum, and Layered Belief-Propagation decoders, with a bit error rate (BER) as low as$4 \times 10^{-8}$at a signal-to-noise ratio (SNR) of 4dB. Furthermore, the proposed LDPC decoder attains a normalized energy efficiency (NEE) of 1.29 pJ/bit/iteration, surpassing the state-of-the-art decoders by a minimum factor of 2.4 and as much as 7.6 times.

Physical Ising machines have been shown to solve combinatoric optimization problems with orders-of-magnitude improvements in speed and energy efficiency o ver v on N eumann systems. However, building such a system is still in its infancy and a scalable, robust implementation remains challenging. CMOS-compatible electronic Ising machines (e.g., [1]) are promising as the mature technology helps bring scale, speed, and energy efficiency to the dynamical system. However, subtle issues can arise when using voltage-controlled transistors to act as programmable resistive coupling. In this paper, we propose a version of resistively-coupled Ising machine using quantized nodal interactions (QuBRIM), which significantly i mproved the predictability of the coupling resistor. The functionality of QuBRIM is demonstrated by solving the well-known Max-Cut problem using both behavioral and circuit level simulations in 45 nm CMOS technology node. We show that the dynamical system naturally seeks local minima in the objective function's energy landscape and that by applying spin-fix a nnealing, t he system reaches a global minimum with a high probability.

Nature has inspired a lot of problem solving techniques over the decades. More recently, researchers have increasingly turned to harnessing nature to solve problems directly. Ising machines are a good example and there are numerous research prototypes as well as many design concepts. They can map a family of NP-complete problems and derive competitive solutions at speeds much greater than conventional algorithms and in some cases, at a fraction of the energy cost of a von Neumann computer.

Ising machines and other nature-based computing platforms have recently become attractive due to their potential of outperforming conventional computers when solving problems that involve a large number of competing alternatives, such as combinatorial optimizations. In this paper, a newly proposed resistively-coupled Ising machine with bistable nodes (BRIM) is designed and simulated in a 45nm CMOS process. The performance of the proposed machine is evaluated based on its capability of solving the Max-cut graph problem. A spin-fix annealing technique is applied to help escape local minima and improve the solution quality. Simulation result shows that this technique effectively increases the probability of finding the Max-cut solution by 50.5% and reduces the solution error to 1.73 on average.

Physical Ising machines rely on nature to guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinatorial optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs. Quantum annealers are a prominent example of such efforts. However, existing Ising machines are generally bulky and energy intensive. Such disadvantages may be acceptable if these designs provide some significant intrinsic advantages at a much larger scale in the future, which remains to be seen. But for now, integrated electronic designs of Ising machines allow more immediate applications. We propose one such design that uses bistable nodes, coupled with programmable and variable strengths. The design is fully CMOS compatible for on-chip applications and demonstrates competitive solution quality and significantly superior execution time and energy.

As the demand for better performance in terms of speed and power efficiency of the hardware increases because of the blooming industries such as the Internet of Things (IoT), the science and engineering tries to keep up. IoT is especially interested in faster interaction with the physical world at next to no cost, which is where the value of advancement in the field of A/D converters can be truly seen. Successive Approximation A/D converters (SA-ADC) have proven to be a solid solution for moderate speed and moderate resolution needs, at the same time consuming low power. However, the traditional SA-ADC needs N cycles to convert analog input signal to N-bit digital signal. Our proposed conversion method brings down the number of cycles to only one when configured properly, employing the concepts of oversampling and predicting the next value of the input signal. This can ultimately increase the speed of the SA-ADCs N-fold keeping the same power consumption, or even lower the power consumption when the signal has a narrow bandwidth. The proposed design is done with compatibility and cost-effectiveness in mind, so that it may be easily implemented in any currently existing SA-ADC designs.

A multi-bit Delta-Sigma ADC employing a nonlinearity suppressed feedback DAC is presented in this paper. Methodologies for a mismatch-insensitive design are proposed and investigated. Measurement results from prototypes fabricated in a 0.13μm process demonstrate that without dynamic-element-matching or calibration techniques, the Delta-Sigma modulator employing a 7-level feedback DAC achieves a SFDR of 94-dB at a sampling rate of 2-MHz. The differential input signal swing is 1 Vpp. Its dynamic range is 81-dB. Peak SNR and SNDR are 79-dB and 75-dB for a bandwidth of 20 Hz-25 kHz, respectively.

A novel architecture for a CMOS image sensor that incorporates a column-level sigma-delta (ΣΔ) analog-to-digital converter is presented. An indirect-feedback readout architecture where the digital output of the ΣΔ modulator is accumulated by a digital counter and converted to an analog voltage that serves as the reference voltage to which the buffered photodiode voltage is compared is shown. A time-domain pixel simulator that enables assessment of major noise contributors in this type of imager is also presented. Theoretical calculations align with simulation results, showing a minimum readout noise of 2.18e- and a dynamic range of over 100dB. A prototype chip has been developed in TSMC's 0.35-μm technology and its performance will be assessed.

We investigate modulation-based parallel delta-sigma (ΔΣ) converters for wideband A/D conversion applications. A code division parallel ΔΣ conversion method is proposed, where each path consisting of a ΔΣ modulator operates on an input signal modulated with different binary code. In contrast to standard Hadamard based modulation schemes, the design provides flexibility in choosing the number of parallel paths and the type of binary modulation sequences. We exploit the information-theoretical approach to design an iterative probabilistic decoding procedure for optimal decoding of the ΔΣ modulator outputs. To demonstrate the decoding method, a maximum a posteriori probability decoder for the first order ΔΣ modulator is developed. Simulation results verify the iterative decoding procedure, demonstrate the use of arbitrary number of paths, and show that the A/D converter based on pseudo-random sequences achieves improved spurious-free dynamic range.

We propose a low-power active switched-capacitor (SC) implementation of the loop filter for PLL applications. Control voltage ripples caused by current mismatches are eliminated. Sub-threshold inverters are employed as the active components of the filter resulting in very low circuit power consumption. Moreover, 1/f noise of the inverter amplifier is suppressed by the SC auto-zeroing. Transistor level simulation of a 2.4-GHz frequency synthesizer in a 0.18 μm technology is carried out to verify the proposed loop filter. With a 10 MHz input reference frequency, the sub-threshold inverter amplifier consumes about 110 uA with a 1.25 V power supply.

We consider optimal power allocation for wireless video sensors (WVSs), including the image sensor subsystem in the system analysis. By assigning a power-rate-distortion (P-R-D) characteristic for the image sensor, we build a comprehensive P-R-D optimization framework for WVSs. For a WVS node operating under a power budget, we propose power allocation among the image sensor, compression, and transmission modules, in order to minimize the distortion of the video reconstructed at the receiver. To demonstrate the proposed optimization method, we establish a P-R-D model for an image sensor based upon a pixel level sigma-delta (Σ∆) image sensor design that allows investigation of the tradeoff between the bit depth of the captured images and spatio-temporal characteristics of the video sequence under the power constraint. The optimization results obtained in this setting confirm that including the image sensor in the system optimization procedure can improve the overall video quality under power constraint and prolong the lifetime of the WVSs. In particular, when the available power budget for a WVS node falls below a threshold, adaptive sensing becomes necessary to ensure that the node communicates useful information about the video content while meeting its power budget.

We propose a CMOS image sensor pixel readout method that eliminates the need for external correlated double sampling circuit that is used in existing CMOS active pixel sensor (APS) design. The pixel transistor count in the proposed design is equal to the standard APS thus retaining high fill factor. The design employs reconfigurable differential-input readout amplifier that may be used in both the reset and the readout phases of the image sensor operation. In the proposed method, the DC offset is removed, flicker noise is differentiated, and reset noise is greatly reduced by employing the amplifier in an active reset configuration. Gain related fixed pattern noise (FPN) is also reduced by higher open-loop gain of the differential amplifier. We present analysis and simulations of the proposed reconfigurable active pixel sensor (RAPS) design in a standard 0.35 mum CMOS process operating from a 3.3 V power supply.

We propose an analog CMOS image sensor with 10X faster readout settling time than standard active pixel sensor (APS) designs. The pixel in the proposed design is a standard APS source follower configuration thus retaining high fill factor. Negative feedback is applied to the readout of the pixel from a column shared circuit to increase its current driving capabilities and thereby reduce the settling time between correlated double sampling (CDS) samples, which significantly reduces the 1/f noise contributed by the in-pixel source follower transistor. In addition, we describe an improved active reset utilizing the current sensing method. We present analysis and simulations of the proposed current sensing active pixel (CSAP) sensor design in a standard 0.35 um CMOS process operating from a 3.3 V power supply.

This paper presents a method to reduce the effects of substrate noise and nonlinear amplifier gain on sigma-delta (ΣΔ) modulators through the use of blue-noise modulation. In addition to reducing the effects of substrate noise and nonlinear amplifier gain, the proposed architecture also suppresses the effects of integrator opamp non-idealities, such as 1/f noise and DC offset, and DAC DC offset and even-order nonlinearities. The architecture proposed herein is referred to as the blue-noise ΣΔ modulator. An example utilizing a third-order blue-noise ΣΔ modulator with a 1-bit quantizer is presented. Additionally, a method to generate the required blue-noise modulation sequence is proposed. Simulation results demonstrate that this architecture achieves an 8.8dB improvement in SNDR over the traditional third-order ΣΔ modulator.

In this paper we describe an image sensor with nonuniform pixel placement that enables a highly efficient computation of the discrete cosine transform, which is the most computationally demanding step of the image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which we show to be 5 times more computationally efficient than currently used DCT computation methods. The architecture and circuits described can be implemented in conventional CMOS processes.

We present a method for substrate coupling noise suppression that employs a pseudo-random clock. A pseudo-random sequence is utilized to randomize the pulse train of the system periodic clock effectively decorrelating its discrete spectral tones. Therefore, the discrete portion (spectral spikes) of the power spectral density of the regular clock is dispersed and the continuous (wide-band) portion of the spectrum rises as a noise floor. This work shows that there is a 22dB attenuation of the harmonic power by utilizing the clock randomization method with respect to the standard clocking scheme where the periodic clock signal is deployed.

In this paper, we present a method to reduce the effects of substrate noise on bandpass sigma-delta (SigmaDelta) ADCs through the use of band-stop noise modulation, where the notch of the modulation noise spectrum is centered around the input signal band. Several band-stop noise (BSN) resonator structures required for bandpass SigmaDelta ADC implementations are presented. The proposed designs have been adapted from traditional resonator designs. These include the forward Euler (FE) resonator, forward Euler non-delayed (FEND) resonator, lossless discrete integrator (LDI), and the double-delay resonator. An example utilizing a fourth-order BSN modulated bandpass SigmaDelta ADC with a 1-bit quantizer is presented. Additionally, a method to generate the required BSN sequence is proposed. Simulation results demonstrate that this architecture achieves a 7.7 dB improvement in SNR and a 19 dB improvement in SFDR over the traditional fourth-order bandpass SigmaDelta ADC

We present a pseudo-two-path bandpass sigma-delta (SigmaDelta) modulator design that improves upon current designs by completely suppressing the mirror image in the input signal band. The proposed SigmaDelta modulator structure introduces a resonator consisting of four total paths that are selected in a blue-noise manner, which serves to spread the mirror image caused from path mismatch across the entire signal bandwidth. A specific example of a two-path modulator utilizing a modulator based on a pseudo-two-path structure with blue-noise randomized capacitor path selection is described. The proposed design improves SFDR performance over traditional pseudo-two-path designs. Additionally, it is shown that the proposed structure demonstrates SNR improvement over a wide range of practical oversampling ratios. Behavioral simulations of this design show improvements to the SFDR of up to 21 dB and SNR up to 7.9 dB from previous two-path techniques

A method for the efficient interpolation of uniformly sampled discrete time signals is described. The method can be used to interpolate N-dimensional discrete signals such as audio, images, and 3D medical imaging. As opposed to conventional interpolation methods, where uniform zero-insertion (expansion) is performed prior to low-pass filtering, the proposed method inserts zeros in a blue-noise pattern, which has been shown most appropriate for this application. This interpolation method attenuates undesired replicas solely by the act of noisy zero-insertion, resulting in relaxed requirements on the order of the interpolation filter, thereby reducing the required computations. This work shows that an N/sup th/ order blue noise pattern reduces the filter order by N.

Data hiding in media, including images, video, and audio, and in data files is currently of great interest both commercially, mainly for the protection of copyrighted digital media, and to the government and law enforcement in the context of information system security and covert communications. We present a technique for inserting and recovering "hidden" data in audio files. The phase of chosen components of the host audio signal is manipulated in a way that may be detected by a receiver with the proper "key". Without the key, the hidden data is undetectable, both aurally and via blind digital signal processing attacks. The method described is both aurally transparent and robust and can be applied to both analog and digital audio signals, the latter including uncompressed as well as compressed audio file formats such as MP3.

In this work, we present a method for the selection of a subset of nodes in a wireless sensor network whose application is to reconstruct the image of a (spatially) bandlimited physical value (e.g., temperature). The selection method creates a sampling pattern based on blue noise masking and guarantees a near minimal number of activated sensors for a given signal-to-noise ratio. The selection method is further enhanced to guarantee that the sensor nodes with the least residual energy are the primary candidates for deselection, while enabling a tradeoff between sensor selection optimality and balanced load distribution. Simulation results show the effectiveness of these selection methods in improving signal-to-noise ratio and reducing the necessary number of active sensors compared with simpler selection approaches.