This paper proposes convergence enhancement to state-space averaging (SSA) methodology for steady-state and small-signal analysis of high-ratio hybrid DC-DC converters, first using analysis of Double-Step-Down (DSD) topology, including parasitics, as an example, then extending to other hybrid topologies with different numbers of capacitors and inductors. The enhanced SSA method can be used to:1)derive small-signal control-to-output transfer functions, which is essential to optimize the compensator for fast and stable closed-loop operation;2)calculate steady-state inductor currents, output voltage, input current and the voltage(s) across the flying capacitor(s),$V_{CFs}$, which is important to determine steady-state characteristics and performance;3)include circuit non-idealities such as parasitics and timing mismatches; and4)evaluate$V_{CF}$balancing property by the proposed matrix invertibility principle and added constants, and determine whether dedicated$V_{CF}$balancing circuits can be eliminated, which is considered an important benefit with reduced complexity and improved reliability. The theoretical results of DSD are then plotted in MATLAB and verified in simulations using PSIM and Cadence periodic transfer function (PXF) analysis, and measurement results using GaN devices. The simulation and measurement results match well with theoretical analysis. The enhancement is then extended beyond the DSD topology to analyze emerging hybrid topologies with more switched inductors and capacitors, future-proofing its capability to be applicable to new hybrid topologies.

This paper introduces an output Capacitor-Less (Cap-Less) Low-Drop-Out regulator (LDO) design with NMOS pass-transistor, featuring a wide loading range with enhanced power supply rejection (PSR) and transient response. From small-signal perspective, the proposed dual-loop design achieves up to 44.6-MHz bandwidth at heavy load while maintaining stability across the full loading range from 0.1 mA to 300mA by the adaptive biasing and zero compensation techniques. From large-signal perspective, the proposed NMOS Super Source Follower (N-SSF) and small- and large-signal conflict softening filter also enhance the slew-rate for faster transient response. The proposed design is presented with bottom-up considerations and then with overall system analysis. Measurement in 180-nm CMOS shows only an 18-mV undershoot with on-chip 1 mA to 272 mA load transient steps in 100 ns with a 50-pF on-chip output capacitance. At 10 MHz, a measured PSR better than -30dB was also observed from 1-mA and 100-mA loading currents.

This paper introduces a single-inductor 4-phase hybrid switched-capacitor (4PSC) topology for integrated high-ratio direct down conversion suitable for point-of-load applications. The proposed topology consists of a 3-phase 4:1 switched-capacitor stage, reducing the switching node swing to 12-V (1/4 of the input) to significantly reduce switching loss, and an inductor to softly charge and discharge the flying capacitors with an extra phase (hence 4-phase operation) with controlled duty cycle to regulate the output voltage to 1V for direct-down conversion. The converter operates with a 4X effective switching frequency, which reduces the ripple/inductance required or switching frequency for better efficiency. With the same output voltage ripples as double step-down (DSD) and 3-level (3L1P) buck converters, the on-time is 4X that of DSD and 3L1P converters, which reduces the challenges in controller design. Lower-voltage (LV) transistors, such as 12-V devices, can be used in some of the switches to significantly improve efficiency. When compared to DSD and 3-Level converters that are state-of-the-art integrated topologies, with the same inductor, output capacitor, and output ripples in the same BCD process, this design achieves: 1) an efficiency comparable or higher than DSD (e.g., ∼3% higher at 48V-1V/5A); 2) along with using only one inductor instead of two for DSD, which can reduce the cost and increase the power density; and 3) much higher efficiency compared to a 3-level buck converter. The 4PSC topology is verified in simulations, showing peak efficiencies of ∼85% and ∼91% in a 180-nm BCD process with 48V-1V and 48V-2V conversions, respectively.

A half-bridge enhancement-mode GaN driver with closed-loop digital calibration is proposed to regulate the VGSringing to the desired device margin to optimize the slew-rate without compromising reliability. The highside and lowside have independent calibration loops for maximum flexibility, each with 8-bit resolution to cover a wide range of package inductance from 200 pH to 2 nH and GaN devices from as small as EPC2036 to as large as EPC2204. A limited bootstrap driver and a shoot-through guarded negative rail are also included to avoid overvoltage during deadtime periods and false turn-on during Miller plateau periods. This work is designed in a 180-nm BCD process and simulated to verify its functionality under different PVT corners and with different parasitic inductance and EPC GaN transistors. The envelop peak detector, which is the core component that determines the accuracy of ringing regulation, shows a maximum error of 6.2% over PVT corners up to 1 GHz of ringing frequency.

In this paper, a 6.78MHz GaN-based full-bridge active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) is proposed. The design features a bootstrap driver to actively switch the high-side GaN transistors, as well as real-time calibration loops to automatically compensate the circuit delays in the low-side control paths, such that the PCE and VCR are maximized with eliminated reverse current and optimal conduction time. The proposed active rectifier is designed and simulated in a 180nm BCD process, and verified under process, voltage and temperature (PVT) variations with power capacity from 20 to 180 W. Thanks to the proposed calibration loops, up to 25% and 20% PCE and VCR improvements, respectively, are observed under various PVT and loading conditions, with a peak PCE of 94.1% at 90-W output power and a peak VCR at 98% at 20-W output power.

A systematic analysis of 3-level integrated buck converters is conducted in this paper. Detailed derivations of the working principles, voltage conversion ratio and output voltage ripple are given. In particular, the system loop gain of 3-level buck converters is analyzed, which provides guidance on designing fast and robust 3-level converters. The derived loop gain is verified with time-domain small signal injection analysis. The results show a good match between analytical and simulation results.

This paper proposes a High-Side (HS) NMOS power switch and bootstrap driver with DCM charging phase extension for high-frequency fully-integrated converters with 1.2V supply voltage. The conventional bootstrap diode is replaced by a self-synchronized switch and the efficiency loss and operation failure at DCM is prevented by an extra charging phase. Simulation at 100MHz with UMC 0.13μm process shows that the optimum efficiency is driven 2% higher with significant power loss reduction by the proposed design compared to a conventional converter under similar operation conditions. 20% power stage area is saved by the dual NMOS structure compared to the conventional converter with PMOS and NMOS switches.

A 4-transistor (4-T) CMOS voltage reference with two high PSRR output voltages is presented. The output voltages are equal to the scaled voltage difference of two threshold voltages at absolute zero temperature. The temperature coefficients' (TCs) difference of the two threshold voltages is compensated by another transistor-size-controlled temperature coefficient to achieve zero TC outputs. A CMOS voltage reference with 0.5V-1.2V supply voltage, two output voltages of 182mV and 85.5mV, is implemented with a 0.13μm CMOS process. Simulation results show that temperature coefficients of 32ppm/°C and 52.5ppm/°C from 0 to 100 °C, and line sensitivities of 0.095%/V and 0.104 %/V are achieved for the two reference voltages, respectively. The supply current is 3nA under all the supply voltage range at room temperature. Moreover, the power supply rejection ratios (PSRRs) of two outputs are -63.83dB and -70.4dB at 100Hz, and -77dB and -98dB at 100kHz, respectively.

A Single-Inductor-Dual-Output (SIDO) buck converter with Cross-Regulation-Suppression (CRS) control scheme is presented. The converter operates in continuous-conduction-mode (CCM) and employs ordered-power-distributive control (OPDC) to distribute the inductor current to the two outputs. The novel CRS control method is used to suppress the cross-regulation (CR) of the SIDO which is an important issue in OPDC CCM converter design. On-chip type-III compensator is incorporated in the SIDO converter to eliminate off-chip components and accelerate system response. The CRS controlled converter is fabricated with AMS 0.35μm CMOS process and operates at 2MHz. Measurement results show that this converter achieves a cross-regulation down to 0.056mV/mA with 180mA load current changes and a response time less than 20μs. The maximum efficiency is 91.8%.