Abstract: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore the proposed technique easily fits in the existing industrial design flows.

An automatic modeling technique is presented in this paper that allows to build an accurate model of power consumption in embedded memory blocks. A software neural-network is used to create a regression tree by automatically splitting those variables that have a discontinuous effect on the power consumption. An application of the methodology to the modeling of a 0.35µm CMOS embedded SRAM is presented.

Introduces the application of an analog associative memory chip to word recognition, which is a fundamental topic of the text recognition process. The word recognition method takes advantage of a statistical evaluation of the behavior of the optical character recognition system preceding it. That statistical information leads to the creation of a coding that is used to store a lexicon of the most used words in the chip. An input pattern is matched against the full database of the associative memory, and a set of closest patterns is returned. The precision reached by this operation ranges from 93% to 99%. These encouraging results demonstrate the general aptitude of the chip to solve classes of problems that need to use an associative memory.