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Steven W. Burns

dblp:83/6431 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 100%
Theoretical computer science
1 paper
Coding theory · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error detection
concurrent error detection
0.011994
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme · IEEE Trans. Computers 1994
Hardware reliability and fault tolerance › self-checking circuits
totally self-checking checker
0.011994
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme · IEEE Trans. Computers 1994
Coding theory › error-correcting codes › error detection
unidirectional error detecting codes
0.011994
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

modular checker design · 0.0codeword test set analysis · 0.0
YearPublicationVenuePosition
1994 A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme
abstract
Bose has developed a parallel unordered coding scheme using only r checkbits for 2/sup r/ information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all zeros and all ones need to be transformed to two other information symbols. This allows one to reduce the number of checkbits over Berger code by 1. Since information symbols containing a power-of-two number of bits are quite common, this coding scheme should become quite popular. The authors describe a modular, economical, and easily testable totally self-checking (TSC) checker design for the above code. The TSC concept is well known for providing concurrent error detection of transient as well as permanent faults. The design is self-testing with at most only 2r+16 codeword tests. This means that if k is the number of information bits, the size of the codeword test set is only O(log/sub 2/ k). This is the first known TSC checker design for this code.>
Steven W. Burns, Niraj K. Jha
IEEE Trans. Computers1
1992 A totally self-checking checker for a parallel unordered coding scheme
abstract
Bose has developed a parallel unordered coding scheme using only r checkbits for 2/sup r/ information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all-0's and all-1's need to be transformed to two other information symbols. This allows one to reduce the number of checkbits over Berger code by 1. Since information symbols containing a power-of-two number of bits are quite common, this coding scheme should become quite popular. In this paper, a modular, economical and easily testable totally self-checking (TSC) checker design for the above code is described. The TSC concept is well-known for providing concurrent error detection of transient as well as permanent faults. The design is self-testing with at most only 2r+16 codeword tests. This means that if k is the number of information bits, the size of the codeword test is only O(log/sub 2/k). This is the first known TSC checker design for this code.>
Steven W. Burns, Niraj K. Jha
VTS1