This article presents a design approach for the modeling and simulation of ultralow power (ULP) analog computing machine learning (ML) circuits for seizure detection using electroencephalography (EEG) signals in wearable health monitoring applications. In this article, we describe a new analog system modeling and simulation technique to associate power consumption, noise, linearity, and other critical performance parameters of analog circuits with the classification accuracy of a given ML network, which allows to realize a power and performance optimized analog ML hardware implementation based on diverse application-specific needs. We carried out circuit simulations to obtain nonidealities, which are then mathematically modeled for an accurate mapping. We have modeled noise, nonlinearity, resolution, and process variations such that the model can accurately obtain the classification accuracy of the analog computing-based seizure detection system. Noise has been modeled as an input-referred white noise that can be directly added at the input. Device process and temperature variations were modeled as random fluctuations in circuit parameters, such as gain and cut-off frequency. Nonlinearity was mathematically modeled as a power series. The combined system level model was then simulated for classification accuracy assessments. The design approach helps to optimize power and area during the development of tailored analog circuits for ML networks with the ability to potentially trade power and performance goals while still ensuring the required classification accuracy. The simulation technique also enables to determine target specifications for each circuit block in the analog computing hardware. This is achieved by developing the ML hardware model, and investigating the effect of circuit nonidealities on classification accuracy. Simulation of an analog computing EEG seizure detection block shows a classification accuracy of 91%. The proposed modeling approach will significantly reduce design time and complexity of large analog computing systems. Two feature extraction approaches are also compared for an analog computing architecture.

Advances of machine learning algorithms have led to improvements of seizure detection capabilities in monitoring systems based on electroencephalography (EEG). Seizure detection hardware requires accurate feature extraction, which is conventionally done in the digital domain by extracting power in different EEG frequency bands over a particular time window. This paper presents an analog counterpart to digital feature extraction. A received signal strength indicator (RSSI) circuit is used for extracting EEG power features in the analog domain. A high-precision RSSI circuit was designed in the sub-threshold domain with ultra-low power consumption and low sensitivity to process-voltage-temperature variations with CMOS technology. Simulation results show that the RSSI circuit consumes 24 nW power, and has a dynamic range of 53 dB with a linearity error of ± 0.5 dB, sufficient to accurately extract features for seizure classification. The analysis of 16 hours of patient EEG data indicates a seizure classification accuracy of 94%, and a non-seizure classification of 86%.