Hyperconvergence is a software-centric architecture which has disrupted the datacenter industry in a dramatic way by bringing the disparate areas of compute, storage and networking into a single system. A hyperconverged system allows the integrated technologies to be managed as a single system through a common tool set. By overcoming the barriers to change and progress created by traditional silos, the hyperconverged infrastructures have been delivering major benefits in terms of power consumption, performance and total cost of ownership.

A Lithography Friendly Design solution entails the creation of a single physical layout which satisfies design constraints while concurrently accounting for process and manufacturing variations. At 45nm and below, above and beyond exponential growth in complexity (and mask-size), Optical Proximity Correction fails to render certain layout topologies. Thus a degree of Lithography Friendly Design (via a lithography metric) and awareness has to be built into physical-design. The current pattern of geometric growth in classic Design Rule Checks (to help OPC), their interdependence, and ranged-interpretation strongly indicates the need for a top-down fabrication-aware physical-design methodology. Even the simple assumption about local-placement context-independence of cells is no longer valid. The mere adjacency of certain standard cells leads to degradation in yield and performance. Thus, even the domain of standard-cell placement and optimization, physical-synthesis, is affected by these lithographic phenomena

As 65nm ramps up towards production and 45nm test-chip trials get under-way, three critical design challenges have emerged:

The advent of 90nm and 65nm technology nodes caused design teams to face a concurrent "3-on-1" assault of massive designs, significant increase in functional requirements, and substantial process modeling complexities. While existing solutions have done well in carving out their niches by solving just one of these three challenges, they impose significant user intervention and manual iterations for the rest. The current crop of EDA tools were not developed to handle the 50M-gate capacity offered by a 90nm die. The sheer complexity of the design functionality coupled with process variations has proven them inadequate for design closure. Finally, the lack of implicit support for variability routinely produces chips with sub-optimal yield. New approaches to achieve closure for multi-million gate designs, with rapid execution times, and accurate modeling of pervasive process effects are needed for these technology nodes. We will discuss the salient engineering and technological challenges of building such a system and provide insights into design trade-offs that will help us achieve this seemingly "holy grail" of digital physical design.

Design routability is a major concern in the application-specific design flow, particularly with today's increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed net list. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are its accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with postroute congestion and present experimental results of subsequent congestion minimization based on this algorithm.

Design routability is a major concern in the ASIC design flow, particularly with todays increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance, and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed netlist. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with post-route congestion, and show experimental results of subsequent congestion optimization based this algorithm.

Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters.Technology decomposition is the step that transforms arbitrary networks to this form.Typically, such decomposition schemes ignore the fact that certain circuit elements can be mapped more eciently by treating them separately during decomposition.Multiplexers are one such category of circuit elements.They appear very naturally in circuits, in the form of datapath elements and as a result of synthesis of CASE statements in HDL speci cations of control logic.Mapping them using multiplexers in technology libraries has many advantages.In this paper, we give an algorithm for optimally decomposing multiplexers, so as to minimize the delay of the network, and demonstrate its eectiveness in improving the quality of mapped circuits.

In this paper, we describe the correlation assumptions made by different power analysis methods and evaluate the impact on the accuracy of total power dissipation calculation as well as of the power dissipated by individual signals. Industrial circuits and applications are used. The results show that some assumptions cause inaccuracies of more than 100% for certain circuit types.

Abstract — In most logic synthesis systems, technology mapping to a target technology is performed using structural matching techniques. Recently there has been a lot of interest on the usage of boolean techniques to do matching of combinational logic. In this paper, we present an extension of boolean matching to perform technology mapping of sequential elements. The new technique is capable of recognizing the presence of complex sequential elements including JK flip-flops, multiplexed flip-flops, flip-flops with asynchronous behavior and complex latches. The underlying algorithm uses a notion of “timed ” variables and relies on a fast boolean matching technique to achieve efficiency. We have implemented these ideas in a simple technology mapper and contrast the results with two other sequential mapping techniques. I.