Progressive low-density parity check (LDPC) code decoding has been widely used to correct increasing raw bit errors in NAND Flash memory. Once the decoding of a single logical page fails, the read-retry operation will reprocess at an increased read level with more accurate initial log-likelihood ratio (LLR) messages. However, the traditional progressive LDPC decodings with inappropriate read-level-increase granularities of read-retry operations introduce unnecessary flash read latency. By taking advantage of globally coupled LDPC (GC-LDPC) codes, an improved adaptive granularity progressive LDPC decoding (IAGPD) is proposed. This method can estimate the number of uncorrectable bit errors before each read-retry operation by detecting the unsatisfied local parity checks and general syndrome in the decoding failure. Then, it adaptively selects the optimal read-level-increase granularities for read-retry operations in the progressive LDPC decoding. Compared with the existing decoding methods, only by an extra 0.098% of the decoder area and two clock cycles, our method can reduce the flash read latency by up to 43%. And the solid-state drive (SSD) read response time on MQsim can be reduced by up to 32%.

This article presents a 60-mode high-throughput parallel-processing memory-based fast Fourier transform (FFT) processor for fifth-generation (5G)/4G applications. The proposed architecture adopts a multi-FFT parallel-processing scheme to significantly reduce the idle computation cycles of small point FFT due to the deep pipeline. The proposed scheme can narrow the throughput gap between different FFT sizes. In conjunction with the parallel processing scheme, a configurable 16-parallelism butterfly unit is proposed to support a maximum of five radix-3, four radix-4, three radix-5, two radix-8, or one radix-9 operation in one cycle. Furthermore, this article demonstrates conflict-free memory access with a parallel method based on fusion shift combined with a hopping-based method to simplify the data arrangement at different radix stages. According to the orthogonal frequency division multiplexing (OFDM) application characteristics, our processor is extended to support many additional commonly used functions, such as zero padding, cyclic prefix insertion, and 7.5-kHz frequency shift, which can simplify the system call in 5G/4G applications. The FFT processor has been successfully integrated into a small-cell base station baseband system-on-chip (SoC) and taped out at the TSMC 12-nm technology. The implementation result reveals that the die area of the proposed processor is 0.374 mm2 with a power consumption of 235.5 mW at 1 GHz, and the processor supports a balanced throughput up to 3.92 GS/s at all 60-mode, which is better than that of the state-of-the-art (SOTA) designs.