Neural-network-driven (NN-driven) network functions and their implementation on the data plane are emerging topics due to demonstrated accuracy and high performance. Meanwhile, we argue that deploying NN-driven network functions should satisfy two design goals: the generality to support various NN models, and the flexibility to operate various network functions. Unfortunately, existing work cannot satisfy both goals simultaneously. In this paper, we introduce the concept of the Intelligent Plane for NN-driven network functions, and propose DP4C, a cross-plane SoC architecture that integrates the intelligent, control, and data planes within a single chip. DP4C comprises the programmable NN inference engine that iteratively executes inference to ensure model generality in the intelligent plane, a multi-core RISC-V CPU that parses inference results into diverse network functions through its architectural flexibility in the control plane, and the switch fabric in the data plane. To further eliminate the performance bottleneck, we propose (i) the direct register access mechanism coupled with custom instructions to reduce the overhead of cross-plane data migration; and (ii) the multi-core pipelining with adaptive batch-processing for multi-core CPU. DP4C SoC is fabricated using 130 nm technology and has already been deployed in industrial IoT environments. We also design three distinct test cases to evaluate DP4C, fully demonstrating the model generality and operational flexibility.

More processors are integrated into Industrial Internet-of-Thing gateways to perform increasing emerging applications. Network-on-chip (NoC) offers a scalable, high-throughput, and energy-efficient communicate infrastructure. However, existing NoC routers cannot guarantee differentiated quality-of-service (QoS) for diversified applications. Hence, we propose a novel NoC router architecture with the gate control mechanism to provide customized QoS.

Time-Sensitive Networking (TSN) is a promising open-source technique for hard real-time embedded fields such as industrial automation and autonomous driving. The embedded end-system deployed in TSN must guarantee deterministic latency and jitter for network I/O in above scenarios. Recent researchers focus on eliminating jitter but neglect to reduce latency. The network I/O latency is still too high to satisfy the dozen-microsecond requirements of latency-sensitive applications. We observed that (1) the data path from registers to external storage is actually the bottleneck for latency reduction, and (2) the serial processing of CPU and NIC can be further optimized. Therefore, we proposed DRA (Direct Register Access), a novel network I/O mechanism to achieve microsecond-level latency. DRA delivers whole packet data from the NIC directly into extended registers inside the CPU, avoiding the waste of time to move data between internal registers and external storage. Moreover, DRA promotes parallelization of CPU processing and NIC transfer to reduce latency. Considering the increasing popularity of RISC-V ISA in embedded systems, we prototype DRA using an open-source RISC-V core on FPGA and evaluate it under real-life application scenarios. Compared with existing mechanisms, experimental results demonstrate that DRA reduces the network I/O latency and jitter by at least 60% and 30%, achieving microsecond-level network I/O processing.

Distributed real-time systems (DRTSs) composed of many embedded end-systems have been widely adopted in the industrial fields. Time-sensitive networking (TSN), as a promising communication infrastructure for DRTS, has shown great potential in industry and academia. TSN assumes that an end-system can release critical tasks to process critical packets strictly according to the prescheduled time. Unfortunately, two factors currently damage this assumption: 1) the jitter caused by system architecture during task release, task execution, and packet transmission; and 2) a TSN schedule result may exceed the execution capability of the end-system and cause conflicts. This article proposed deterministic chip (DetChip), a system-on-chip capable of deterministically implementing the TSN schedule result. DetChip supports time-triggered task release, time-predictable task execution and precise network transmission. Based on DetChip, this article first formalizes the execution capability of the end-system as end-system constraints (ECs). Existing TSN scheduling algorithms integrating ECs can solve conflicts by co-scheduling end-systems and the TSN network. Compared with previous works, DetChip only introduces few clock cycles jitter for critical task execution according to the TSN schedule result. The proposed ECs obtain$2\times$–$8\times$more conflict-free solutions for advanced scheduling algorithms with a linear increase in time overhead. Compared with the general end-system, DetChip can reduce$6\times$–$20\times$processing jitter to achieve better clock synchronization.

FPGA is widely used in real-time network processing such as packet classification in SDN switches due to high performance and programmability. BV-based approaches on FPGA provide a performance guarantee for multi-field packet classification, but no update latency guarantee. We thus present SplitBV for the efficient update by splitting the ruleset into subrulesets that can be performed in parallel. Results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow1.0 rules respectively.

The high-performance hardware architectures for multi-field packet classification have been studied over the past decade. Although many FPGA-based solutions can achieve very high throughput, the limited FPGA resources severely hinders the scalability of the rulesets or matching fields. To address this issue, we present a parallel architecture named Wildcard-removed Two-dimensional Pipeline (WeeTP) to save memory usage of wildcards and reduce logic resources. WeeTP uses the Maximum Wildcard Overlap (MWO) algorithm to maximize the compression percentage by rearranging the ruleset. We implement and evaluate WeeTP on an Intel STRATIX V FPGA. Experimental results show that our approach can save 37% and 41% memory consumption on average for real 5-tuple rules and OpenFlow rules, respectively.