Demo Data from EDBT 2026 / reviewers in the wild / expert
Shalom Goldenberg
dblp:83/785
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines
binary translation |
0.0 | 1 | 2003 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems · MICRO 2003 |
Runtime systems and virtual machines › binary translation
dynamic translation |
0.0 | 1 | 2003 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems · MICRO 2003 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 2003 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems · MICRO 2003 |
Methods — techniques the papers use, named apart from their topics
two-phase translation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Java JNI Bridge: A Framework for Mixed Native ISA ExecutionabstractManaged runtime environments (MRTEs) such as the Java platform promise a cross platform "write once, deploy anywhere" mechanism. However, MRTE applications that contain native method calls are not seamlessly portable across platforms. In this paper, we describe a new approach to transparently run Java applications containing native method calls to one ISA (instruction set architecture) on a different ISA's Java platform. This approach operates within the same operating system process that executes the application but with the support of a dynamic translator. This paper describes the technical challenges and solutions of such an in-process implementation within a production Java Virtual Machine (JVM). These include interfacing the JVM with a dynamic translator to support native calls to a different ISA, pursuing a JVM-independent implementation, enhancing the dynamic translator to support shared libraries in addition to executables, marshalling arguments across ISA boundaries, and providing full support for all Java features such as multi-threading. The paper presents performance results for an end-user application, showing our approach to be 2-3 times faster than other approaches. Miaobo Chen, Shalom Goldenberg, Suresh Srinivas, Valery Ushakov, Young Wang, Eric Lin, Yoav Zach |
CGO | 2 |
| 2003 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systemsabstractIA-32 execution layer (IA-32 EL) is a new technology that executes IA-32 applications on Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium-based platforms is achieved using hardware circuitry on the Itanium processors. This capability will be enhanced with IA-32 EL - software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation. In this paper, we describe aspects of the IA-32 execution layer technology, including the general two-phase translation architecture and the usage of a single translator for multiple operating systems. The paper provides details of some of the technical challenges such as precise exception, emulation of FP, MMX, and Intel streaming SIMD extension instructions, and misalignment handling. Finally, the paper presents some performance results. Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yigel Zemach |
MICRO | 4 |