The openness of underwater wireless sensor networks (UWSNs) exposes them to potential eavesdropping attacks, enabling attackers to trace back and identify the source nodes of packet flows. This poses a significant threat to the confidentiality of sensitive applications, known as the Source Location Privacy (SLP) problem. Conventional packet encryption methods are ineffective in defending against SLP attacks since attackers do not need to know the content of the packets. A commonly used method to address the SLP problem is to establish fake transmission paths, making attackers follow fake paths and thus extending the time required to trace back to the source node. Existing SLP solutions that use fake transmission paths only consider individual source nodes, where the fake paths constructed for different source nodes are independent and cannot cooperate to resist attacks. In this paper, a Fake Path Co-Construction source location privacy protection protocol (FPCC) suitable for UWSNs is proposed. FPCC combines the existing transmission paths and creates co-constructed fake paths to simultaneously protect two source nodes. Simulation results confirm that FPCC, when compared with existing well-performed SLP protection protocols, extends safety time without increasing the number of nodes involved in transmitting fake packets.

In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. For a set of linear-pipelined real-time tasks (each with same deadline) and a set of processors (or hosts), we discuss how to develop an energy-efficient resource-allocation scheme to assign processors (or hosts) to handle the tasks and set the processor speed properly so that all tasks can be completed by a given deadline and with minimal energy consumption. We propose an O(m/sup 2/logm) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given m real-time tasks running on n identical processors (with or without DVS supports). Also, an O(min(n/sup 2/m/sup 2/, nm/sup 2/logm)) time complexity algorithm is proposed for systems with an array of n heterogeneous processors in fixed order.

In this paper, we extend previous works on the problem of mapping pipelined (chain-like) computation modules onto a set of (chain-like) linear array processors. We show how this problem can be solved more effectively by pre-filtering out those bad partition points, which can be determined by the proposed forward-backward filtering scheme. By eliminating those infeasible (bad) partition points, some modules can be merged virtually and thus the total number of modules to be considered is reduced. Consequently, search speed is accelerated Meanwhile, the sub-chain cost matrix, formed by the new module set after above filtering and merging scheme, can be proved being well (lattice-like) ordered. This elegant property avoids the need of matrix rearrangement while applying the two dimension binary search method to find optimal solutions.

We present an experience of using FPGAs in the design and implementation of a multicomputer interconnection network. The switching element, the router and the network controllers are all designed and implemented with FPGAs, and cooperatively form a four port by four port interconnection network. The switching elements were designed with ASIC before, but were not very successful. Advantages of using FPGAs over traditional ASIC design are discussed.