Signal processing plays a vital role in various areas of engineering, particularly in industrial automation. Signal processing applications are based on a data flow paradigm, which uses directed graphs to describe the flow of data between operations. Although industrial control applications are based on standards such as IEC 61499, their syntax, and semantics differ from the data flow paradigm, creating a challenge in integrating signal processing applications into industrial automation systems. Modeling signal processing applications using IEC 61499 is not yet a common practice. This paper addresses this gap by proposing an approach to transform data flow models into IEC 61499 models. This approach enables the design and transformation of signal processing applications using data flow models, without requiring manual modeling or knowledge of the IEC 61499 standard. The model transformation is formally defined and subsequently implemented as a separate tool. A running example illustrates the transformation process, demonstrating that the model is both syntactically correct and executable.

While existing hardware runtime monitors for processors are limited in scope and reconfigurability, this paper addresses the need for a flexible and comprehensive monitoring solution. We introduce the Time Contract Co-Processor (TCCP), a reconfigurable open-source co-processor for RISC-V systems. The TCCP uses a formal contract-based notation as input to specify the system’s timing and behavioral requirements. A dedicated toolchain enables the translation of contract micro-programs executed in the TCCP to monitor complex applications.

Extensive compiler support is a key-necessity for the general acceptance and usability of the promising Coarse Grained Reconfigurable Array (CGRA) accelerator architecture. However, there is currently little work to seamlessly connect mathematical graph-based modeling/programming languages and graph-based intermediate representations into a model-based semi-automatic compilation flow in which experts from different domains can collaborate interactively. Therefore, we present a flexible graph language with well-defined execution semantics which facilitates this intended compilation flow by supporting multiple user-defined abstractions. Starting with an abstract mathematical kernel description, we show that different mappings to a modern CGRA can be explored in an under-standable way with our language. We argue that our work is a promising starting point to increase the understandability and accessibility of CGRA compilation.

The Time Sensitive Networking (TSN) standard was introduced to provide deterministic Ethernet-based communication for industrial distributed systems. However, configuration needs to be done manually and is error prone. Combining TSN with the IEC 61499 modeling standard opens up new opportunities for automatic network configuration. A prerequisite is to have an in depth understanding of the requirements for a TSN/IEC 61499 control system and especially of the communication time behavior. We developed a time measurement concept to analyze the timing effects on three important layers under different traffic configurations. We deployed our IEC 61499 implementation on two directly connected Intel I210 evaluation boards based on a minimized Linux Operating System to reduce non-deterministic external influences. The results show the expected effect of using a TSN configuration and a particularly positive impact with TSN transmission windows that are long enough for the IEC 61499 application, especially at the receiving device. The measured delays are shorter for the IEC 61499 application when it is scheduled as time-critical with competing traffic compared to when it runs without a TSN schedule and competing traffic. This is evidence that IEC 61499 performs very well together with a TSN configuration, which opens the door for automatic network configuration in IEC 61499 Ethernet/TSN control applications.

The IEC 61499 standard offers the possibility to model distributed systems, especially in the domain of industrial automation. Since debugging at design time is becoming more and more important and the verification of the execution at event and function block level is becoming more and more important, this paper presents an approach for model-aware simulation of IEC 61499 models in which traces of the event chain can be viewed after simulation time. For this purpose, the information is extracted from the model and transformed into a SystemC model that enables tracing. This SystemC model can also be augmented with existing tools and methods from the SystemC ecosystem, e.g. in order to perform virtual integration testing in a contract-based design flow.

Modern production systems are constantly getting more complex and moving towards smaller lot sizes and more customizable products. This poses new challenges on the control software, which is growing in size and complexity. To deal with this increasingly large and complex control software, design guidelines are needed. We are working on such design guidelines for IEC 61499, a modeling language for distributed control systems. In our previous work, we proposed a distributed and highly reusable application design based on skills. In this work, we will present concepts for extending this design beyond normal operation handling.

In an electronic system level design flow, early timing predictions can be realized by employing virtual platform simulations in the transaction level abstraction. However, there is little research comparing virtual platform solutions for small RISC-V based System-on-a-Chip architectures. This paper tries to fill this gap with a qualitative and quantitative comparison focusing on timing prediction accuracy. Starting with a total list of 25 RISC-V simulators, we found that only three candidates fulfill a comprehensive set of requirements for research applications. For these candidates we performed a quantitative comparison in which we model a single-master bus-based System-on-a-Chip at different abstraction levels and measure each simulator’s timing prediction accuracy and simulation speed.

Real-time communication of distributed automation systems come with many challenges as there is no common time basis. Often a periodic execution of applications is considered which leads to time phenomena like drifts or jitter. Thus, this type of communication requires observance and enforcement of real-time properties to guarantee reliability of distributed systems. New industrial technologies like Time-Sensitive Networking (TSN) and the IEC 61499 standard provide support to conquer upcoming challenges. Therefore, we are using these jointly with contract-based design to propose a design methodology for verification of real-time communication in IEC 61499 systems. We implemented a simulation-based verification environment and performed postmortem trace-based verification against timing specifications. The evaluation confirms the possibility of integrating our proposed representation for non-local communication into IEC 61499 for analyzing time behavior of applications.

The ever rising energy and accordingly cooling demands are a major hurdle for the scalability of today's supercomputers. We are challenged with the need to increase computation performance to cope with the rising complexity of calculations on the one hand and the need to keep the energy/cooling demand stable or in the best case even to reduce it. Recently, one widely discussed way to do this is the integration of heterogeneous computation devices into the supercomputer systems as these tend to have a far better performance/energy ratio for large classes of applications. The obvious drawback of heterogeneous systems is the additional design complexity for the software development in order to efficiently use these devices in terms of performance as well as power. For this reason we propose a flow, which assists the software developer at design time, offering immediate power- and performance-estimation. Such approaches are already known in the embedded world, helping there to select between different design possibilities, and will be used to get the best possible performance from a massively heterogeneous computation platform, while still keeping the energy consumption in mind.