Negative Biased Temperature Instability-induced aging has emerged as one of the critical reliability threats in the nano-era. In this paper, we propose a microarchitectural-level technique for mitigating aging of on-chip SRAM-based memories. The goal is to achieve balanced aging of all memory cells at minimal energy overhead, leading to a longer lifetime. For a configurable and energy-efficient design, we perform aging and energy analysis of different aging balancing circuits. This analysis is leveraged to design a novel energy-efficient anti-aging memory architecture. Our architecture employs a configurable anti-aging controller that leverages the data characteristics to dynamically select (1) at what time instant the aging balancing circuit should be activated, and (2) on which SRAM cells aging balancing should be applied. Our experiments demonstrate significant aging improvements while providing up to 30% energy savings.

This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of- the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4×4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2× higher throughput, while processing HD1080p@30fps.