Single event transient (SET) pulses are a significant cause of soft errors in a circuit. To cope with SET pulses, we propose a new storage cell that is able to operate either as a hard-edge or soft-edge flip-flop depending on the appearance or not of a transition in a time window. The efficiency of the proposed design with respect to the reduction of soft-errors coming from SET pulses was shown with extensive simulations.

Several dictionary-based input test data compression methods have been proposed for intellectual property (IP) cores testing. To increase the utilization of the dictionary entries some methods are based on the correction of some bits before the loading of the entries into the scan chains. The coordinates of the bits that should be corrected are sent by the automatic test equipment (ATE), hence, the number of corrections should be relatively small. In this paper we propose a new method which is based on the use of an auxiliary dictionary of minor size for storing masks. To this end, we give an algorithm for the suitable selection of the masks so that any one of them is used for on the fly bit-flipping of parts of many dictionary entries, before they are loaded into the scan chains. The efficiency of the proposed method is supported with extensive experimental results.

In this paper, we present a new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries. Two approaches are investigated: the static and the dynamic. In the static approach, the content of the dictionary is constant during the testing of a core, while in the dynamic approach the testing of a core consists of several test sessions and the content of the dictionary is different during each test session. The efficiency of the proposed method is supported with extensive simulation results and comparisons to already known test data compression methods suitable for IP cores testing.