Demo Data from EDBT 2026 / reviewers in the wild / expert
Toshiaki Chiba
dblp:84/10970
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
layout verification |
0.0 | 3 | 1982 | Programs for verifying circuit connectivity of mos/lsi mask artwork · DAC 1982 An integrated mask artwork analysis system · DAC 1980 A layout checking system for large scale integrated circuits · DAC 1977 |
Electronic design automation
physical design |
0.0 | 3 | 1982 | Programs for verifying circuit connectivity of mos/lsi mask artwork · DAC 1982 An integrated mask artwork analysis system · DAC 1980 A layout checking system for large scale integrated circuits · DAC 1977 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1982 | Programs for verifying circuit connectivity of mos/lsi mask artwork · DAC 1982 |
Electronic design automation › physical verification
mask verification |
0.0 | 1 | 1982 | Programs for verifying circuit connectivity of mos/lsi mask artwork · DAC 1982 |
Electronic design automation
physical verification |
0.0 | 1 | 1980 | An integrated mask artwork analysis system · DAC 1980 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1980 | An integrated mask artwork analysis system · DAC 1980 |
Electronic design automation › hardware verification and test
logic simulation |
0.0 | 1 | 1980 | An integrated mask artwork analysis system · DAC 1980 |
Methods — techniques the papers use, named apart from their topics
design rule checking · 0.0circuit parameter extraction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | Programs for verifying circuit connectivity of mos/lsi mask artwork
Makoto Takashima, Takashi Mitsuhashi, Toshiaki Chiba, Kenji Yoshida |
DAC | 3 |
| 1980 | An integrated mask artwork analysis systemabstractA new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator. Takashi Mitsuhashi, Toshiaki Chiba, Makoto Takashima, Kenji Yoshida |
DAC | 2 |
| 1977 | A layout checking system for large scale integrated circuits
Kenji Yoshida, Takashi Mitsuhashi, Yasuo Nakada, Toshiaki Chiba, Kiyoshi Ogita, Shinji Nakatsuka |
DAC | 4 |